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cplds at fpga densities? delta39k? isr? cpld fami ly cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-03039 rev. *h revised august 1, 2003 features high density ? 30k to 200k usable gates ? 512 to 3072 macrocells ? 136 to 428 maximum i/o pins ? twelve dedicated inputs including four clock pins, four global i/o control signal pins and four jtag interface pins for boundary scan and reconfig- urability embedded memory ? 80k to 480k bits embedded sram 16k to 96k bits of (dual-port) channel memory high speed ? 233-mhz in-system operation anyvolt? interface ? 3.3v, 2.5v,1.8v, and 1.5v i/o capability low-power operation ? 0.18-mm six-layer metal sram-based logic process ? full-cmos implementation of product term array ? standby current as low as 5ma simple timing model ? no penalty for using full 16 product terms/macrocell ? no delay for single product term steering or sharing flexible clocking ? spread aware? pll drives all four clock networks allows 0.6% spread spectrum input clocks several multiply, divide and phase shift options ? four synchronous clock networks per device ? locally generated product term clock ? clock polarity control at each register carry-chain logic for fast and efficient arithmetic opera- tions multiple i/o standards supported ? lvcmos (3.3/3.0/2.5/1.8v), lvttl, 3.3v pci, sstl2 (i-ii), sstl3 (i-ii), hstl (i-iv), and gtl+ compatible with nobl?, zbt?, and qdr? srams programmable slew rate control on each i/o pin user-programmable bus hold capability on each i/o pin fully 3.3v pci-compliant (to 66-mhz 64-bit pci spec, rev. 2.2) compactpci hot swap ready multiple package/pinout offering across all densities ? 208 to 676 pins in pqfp, bga, and fbga packages ? simplifies design migration across density ? self-boot? solution in bga and fbga packages in-system reprogrammable? (isr?) ? jtag-compliant on-board programming ? design changes do not cause pinout changes ieee1149.1 jtag boundary scan development software warp ? ? ieee 1076/1164 vhdl or ieee 1364 verilog context sensitive editing ? active-hdl fsm graphical finite state machine editor ? active-hdl sim post-synthesis timing simulator ? architecture explorer for detailed design analysis ? static timing analyzer for critical path analysis ? available on windows ? 95/98/2000/xp? and windows nt? for $99 ? supports all cypress programmable logic products delta39k? isr cpld family members device typical gates [1] macrocells cluster memory (kbits) channel memory (kbits) maximum i/o pins f max2 (mhz) speed-t pd pin-to-pin (ns) standby i cc [2] t a = 25 c 3.3/2.5v 39k30 16k ? 48k 512 64 16 174 233 7.2 5 ma 39k50 23k ? 72k 768 96 24 218 233 7.2 5 ma 39k100 46k ? 144k 1536 192 48 302 222 7.5 10 ma 39k165 77k ? 241k 2560 320 80 386 181 8.5 20 ma 39k200 92k ? 288k 3072 384 96 428 181 8.5 20 ma notes: 1. upper limit of typical gates is calculated by assuming only 10% of the channel memory is used. 2. standby i cc values are with pll not utilized, no output load and stable inputs.
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 2 of 86 notes: 3. speed bins shown here are for commercial operating range. please refer to delta39k ordering information on industrial-range s peed bins on page 38. 4. self-boot solution integrates the boot prom (flash memory) with delta39k die inside the same package. this flash memory can e ndure at least 10,000 programming/erase cycles and can retain data for at least 100 years. delta39k speed bins [3] device v cc 233 200 181 125 83 39k30 3.3/2.5v x x x 39k50 3.3/2.5v x x x 39k100 3.3/2.5v x x x 39k165 3.3/2.5v x x x 39k200 3.3/2.5v x x x device package offering and i/o count including dedicated clock and control inputs device 208 eqfp 28 28 mm 0.5-mm pitch 256 fbga 17 17 mm 1.0-mm pitch 484-fbga 23 23 mm 1.0-mm pitch self-boot solution [4] 256-fbga 17 17 mm 1.0-mm pitch 388-bga 35 35 mm 1.27-mm pitch 484-fbga 23 23 mm 1.0-mm pitch 676-fbga 27 27 mm 1.0-mm pitch 39k30 136 174 174 39k50 136 180 218 218 39k100 136 180 302 294 302 39k165 136 356 294 386 39k200 136 368 294 428
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 3 of 86 general description the delta39k family, based on a 0.18-mm , six-layer metal cmos logic process, offers a wide range of high-density solutions at unparalleled system performance. the delta39k family is designed to combine the high speed, predictable timing, and ease of use of cplds with the high densities and low power of fpgas. with devices ranging from 30,000 to 200,000 usable gates, the family features devices ten times the size of previously available cplds. even at these large densities, the delta39k family is fast enough to implement a fully synthesizable 64-bit, 66-mhz pci core. the architecture is based on logic block clusters (lbc) that are connected by horizontal and vertical (h and v) routing channels. each lbc features eight individual logic blocks (lb) and two cluster memory blocks. adjacent to each lbc is a channel memory block, which can be accessed directly from the i/o pins. both types of memory blocks are highly config- urable and can be cascaded in width and depth. see figure 1 for a block diagram of the delta39k architecture. all the members of the delta39k family have cypress?s highly regarded in-system reprogrammability (isr) feature, which simplifies both design and manufacturing flows, thereby reducing costs. the isr feature provides the ability to recon- 4 gclk[3:0] 4 4 4 channel ram 4 gclk[3:0] 4 4 4 4 gclk[3:0] 4 4 4 4 4 gclk[3:0] pll and clock mux gctl[3:0] i/o bank 6 i/o bank 7 i/o bank 3 i/o bank 2 i/o bank 4 i/o bank 5 i/o bank 1 i/o bank 0 lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram channel ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram lb 4 lb 3 lb 0 cluster ram lb 5 lb 6 lb 7 lb 2 lb 1 pim cluster ram figure 1. delta39k100 block diagram (three rows four columns) with i/o bank structure
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 4 of 86 figure the devices without having design changes cause pinout or timing changes in most cases. the cypress isr function is implemented through a jtag-compliant serial interface. data is shifted in and out through the tdi and tdo pins respectively. superior routability, simple timing, and the isr allows users to change existing logic designs while simul- taneously fixing pinout assignments and maintaining system performance. the entire family features jtag for isr and boundary scan, and is compatible with the pci local bus specification, meeting the electrical and timing requirements. the delta39k family also features user programmable bus-hold and slew rate control capabilities on each i/o pin. anyvolt interface all delta39kv devices feature an on-chip regulator, which accepts 3.3v or 2.5v on the v cc supply pins and steps it down to 1.8v internally, the voltage level at which the core operates. with delta39k?s anyvolt technology, the i/o pins can be connected to either 1.8v, 2.5v, or 3.3v. all delta39k devices are 3.3v-tolerant regardless of v ccio or v cc settings. global routing description the routing architecture of the delta39k is made up of horizontal and vertical (h and v) routing channels. these routing channels allow signals from each of the delta39k architectural components to communicate with one another. in addition to the horizontal and vertical routing channels that interconnect the i/o banks, channel memory blocks, and logic block clusters, each lbc contains a programmable inter- connect matrix ? (pim?), which is used to route signals among the logic blocks and the cluster memory blocks. figure 2 is a block diagram of the routing channels that interface within the delta39k architecture. the lbc is exactly the same for every member of the delta39k cpld family. logic block cluster (lbc) the delta39k architecture consists of several logic block clusters, each of which have eight logic blocks (lb) and two cluster memory blocks connected via a programmable inter- connect matrix (pim) as shown in figure 3 . each cluster memory block consists of 8-kbit single-port ram, which is configurable as synchronous or asynchronous. the cluster memory blocks can be cascaded with other cluster memory blocks within the same lbc as well as other lbcs to implement larger memory functions. if a cluster memory block is not specifically utilized by the designer, cypress?s warp software can automatically use it to implement large blocks of logic. all lbcs interface with each other via horizontal and vertical routing channels. note: 5. for hstl only. table 1. device v cc v ccio 39kv 3.3v or 2.5v 3.3v or 2.5v or 1.8v or 1.5v [5] lb cluster pim cluster memory block lb lb lb lb cluster memory block lb lb lb channel memory block i/o block i/o block channel memory outputs drive dedicated tracks in the horizontal and vertical routing channels h-to-v pim v-to-h pim pin inputs from the i/o cells drive dedicated tracks in the horizontal and vertical routing channels 72 72 64 64 figure 2. delta39k routing interface
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 5 of 86 logic block the lb is the basic building block of the delta39k architecture. it consists of a product term array, an intelligent product-term allocator, and 16 macrocells. product term array each logic block features a 72 x 83 programmable product term array. this array accepts 36 inputs from the pim. these inputs originate from device pins and macrocell feedbacks as well as cluster memory and channel memory feedbacks. active low and active high versions of each of these inputs are generated to create the full 72-input field. the 83 product terms in the array can be created from any of the 72 inputs. of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. two of the remaining three product terms in the logic block are used as asynchronous set and asynchronous reset product terms. the final product term is the product term clock (ptclk) and is shared by all 16 macrocells within a logic block. product term allocator through the product term allocator, warp software automati- cally distributes the 80 product terms as needed among the 16 macrocells in the logic block. the product term allocator provides two important capabilities without affecting perfor- mance: product term steering and product term sharing. product term steering product term steering is the process of assigning product terms to macrocells as needed. for example, if one macrocell requires ten product terms while another needs just three, the product term allocator will ?steer? ten product terms to one macrocell and three to the other. on delta39k devices, product terms are steered on an individual basis. any number between 1 and 16 product terms can be steered to any macrocell. product term sharing product term sharing is the process of using the same product term among multiple macrocells. for example, if more than one function has one or more product terms in its equation that are common to other functions, those product terms are only programmed once. the delta39k product term allocator allows sharing across groups of four macrocells in a variable fashion. the software automatically takes advantage of this capability so that the user does not have to intervene. note that neither product term sharing nor product term steering have any effect on the speed of the product. all steering and sharing configurations have been incorporated in the timing specifications for the delta39k devices. . logic block 0 logic block 1 logic block 3 logic block 2 cluster memory 0 pim logic block 7 logic block 6 logic block 4 logic block 5 cluster memory 1 64 inputs from horizontal routing channel 64 inputs from vertical routing channel 144 outputs to horizontal and vertical cluster-to-channel pims clock inputs gclk[3:0] cc cc cc cc cc cc cc = carry chai n 16 36 16 36 16 36 16 36 16 36 16 36 16 36 8 25 8 25 4 16 36 figure 3. delta39k logic block cluster diagram
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 6 of 86 macrocell within each logic block there are 16 macrocells. each macrocell accepts a sum of up to 16 product terms from the product term array. the sum of these 16 product terms can be output in either registered or combinatorial mode. figure 4 displays the block diagram of the macrocell. the register can be asynchronously preset or asynchronously reset at the macrocell level with the separate preset and reset product terms. each of these product terms features programmable polarity. this allows the registers to be preset or reset based on an and expression or an or expression. an xor gate in the delta39k macrocell allows for many different types of equations to be realized. it can be used as a polarity mux to implement the true or complement form of an equation in the product term array or as a toggle to turn the d flip-flop into a t flip-flop. the carry-chain input mux allows additional flexibility for the implementation of different types of logic. the macrocell can utilize the carry chain logic to implement adders, subtractors, magnitude comparators, parity tree, or even generic xor logic. the output of the macrocell is either registered or combinatorial. carry chain logic the delta39k macrocell features carry chain logic which is used for fast and efficient implementation of arithmetic opera- tions. the carry logic connects macrocells in up to four logic blocks for a total of 64 macrocells. effective data path opera- tions are implemented through the use of carry-in arithmetic, which drives through the circuit quickly. figure 4 shows that the carry chain logic within the macrocell consists of two product terms (cpt0 and cpt1) from the pta and an input carry-in for carry logic. the inputs to the carry chain mux are connected directly to the product terms in the pta. the output of the carry chain mux generates the carry-out for the next macrocell in the logic block as well as the local carry input that is connected to an input of the xor input mux. carry-in and a configuration bit are inputs to an and gate. this and gate provides a method of segmenting the carry chain in any macrocell in the logic block. macrocell clocks clocking of the register is highly flexible. four global synchronous clocks (gclk[3:0]) and a ptclk are available at each macrocell register. furthermore, a clock polarity mux within each macrocell allows the register to be clocked on the rising or the falling edge (see macrocell diagram in figure 4 ). preset/reset configurations the macrocell register can be asynchronously preset and reset using the preset and reset mux. both signals are active high and can be controlled by either of two preset/reset product terms (prc[1:0] in figure 4 ) or gnd. in situations where the preset and reset are active at the same time, reset takes priority over preset. d q pset res gclk[3:0] ptclk from ptm cpt0 cpt1 prc[1:0] 0 1 0 1 to pim c carry out (to macrocell n+1) carry in (from macrocell n-1) up to 16 pts preset mux clock polarity mux reset mux clock mux carry chain mux xor input mux output mux q c 3 3 2 3 c c c c c c figure 4. delta39k macrocell
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 7 of 86 embedded memory each member of the delta39k family contains two types of embedded memory blocks. the channel memory block is placed at the intersection of horizontal and vertical routing channels. each channel memory block is 4096 bits in size and can be configured as asynchronous or synchronous dual-port ram, single-port ram, read-only memory (rom), or synchronous fifo memory. the memory organization is configurable as 4k 1, 2k 2, 1k 4 and 512k 8. the second type of memory block is located within each lbc and is referred to as a cluster memory block. each lbc contains two cluster memory blocks that are 8192 bits in size. similar to the channel memory blocks, the cluster memory blocks can be configured as 8k 1, 4k 2, 2k 4 and 1k 8 asynchronous or synchronous single-port ram or rom. cluster memory each logic block cluster of the delta39k contains two 8192-bit cluster memory blocks. figure 5 is a block diagram of the cluster memory block and the interface of the cluster memory block to the cluster pim. the output of the cluster memory block can be optionally regis- tered to perform synchronous pipelining or to register asynchronous read and write operations. the output registers contain an asynchronous reset which can be used in any type of sequential logic circuits (e.g., state machines). there are four global clocks (gclk[3:0]) and one local clock available for the input and the output registers. the local clock for the input registers is independent of the one used for the output registers. the local clock is generated in the user design in a macrocell or comes from an i/o pin. cluster memory initialization the cluster memory powers up in an undefined state, but is set to a user-defined known state during configuration. to facilitate the use of look-up-table (lut) logic and rom applications, the cluster memory blocks can be initialized with a given set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory the delta39k architecture includes an embedded memory block at each crossing point of horizontal and vertical routing channels. the channel memory is a 4096-bit embedded memory block that can be configured as asynchronous or synchronous single-port ram, dual-port ram, rom, or synchronous fifo memory. data, address, and control inputs to the channel memory are driven from horizontal and vertical routing channels. all data and fifo logic outputs drive dedicated tracks in the horizontal and vertical routing channels. the clocks for the channel memory block are selected from four global clocks and pin inputs from the horizontal and vertical channels. the clock muxes also include a polarity mux for each clock so that the user can choose an inverted clock. dual-port (channel memory) configuration each port has distinct address inputs, as well as separate data and control inputs that can be accessed simultaneously. the inputs to the dual-port memory are driven from the horizontal and vertical routing channels. the data outputs drive dedicated tracks in the routing channels. the interface to the routing is such that port a of the dual-port interfaces primarily with the horizontal routing channel and port b interfaces primarily with the vertical routing channel. 5:1 din[7:0] dq addr[12:0] dq cluster pim dq we write pulse write control logic 1024x8 asynchronous sram read control logic row decode (1024 rows) dout[7:0] 8 3 3 8 10 c c d q gclk[3:0] 5:1 r reset gclk[3:0] c local clk 2 local clk 3 2 3 c c c c c c c figure 5. block diagram of cluster memory block
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 8 of 86 the clocks for each port of the dual-port configuration are selected from four global clocks and two local clocks. one local clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs of the dual- port memory can also be registered. clocks for the output registers are also selected from four global clocks and two local clocks. one clock polarity mux per port allows the use of true or complement polarity for input and output clocking purposes. arbitration the dual-port configuration of the channel memory block provides arbitration when both ports access the same address at the same time. depending on the memory operation being attempted, one port always gets priority. see table 2 for details on which port gets priority for read and write opera- tions. an active-low ?address match? signal is generated when an address collision occurs. fifo (channel memory) configuration the channel memory blocks are also configurable as synchronous fifo ram. in the fifo mode of operation, the channel memory block supports all normal fifo operations without the use of any general-purpose logic resources in the device. the fifo block contains all of the necessary fifo flag logic, including the read and write address pointers. the fifo flags include an empty/full flag (ef ), half-full flag (hf ), and program- mable almost-empty/full (paef ) flag output. the fifo config- uration has the ability to perform simultaneous read and write operations using two separate clocks. these clocks may be tied together for a single operation or may run independently for asynchronous read/write (with regard to each other) appli- cations. the data and control inputs to the fifo block are driven from the horizontal or vertical routing channels. the data and flag outputs are driven onto dedicated routing tracks in both the horizontal and vertical routing channels. this allows the fifo blocks to be expanded by using multiple fifo blocks on the same horizontal or vertical routing channel without any speed penalty. in fifo mode, the write and read ports are controlled by separate clock and enable signals. the clocks for each port are selected from four global clocks and two local clocks. one local clock is sourced from the horizontal channel and the other from the vertical channel. the data outputs from the read port of the fifo can also be registered. one clock polarity mux per port allows using true or complement polarity for read and write operations. the write operation is controlled by the clock and the write enable pin. the read operation is controlled by the clock and the read enable pin. the enable pins can be sourced from horizontal or vertical channels. channel memory initialization the channel memory powers up in an undefined state, but is set to a user-defined known state during configuration. to facil- itate the use of look-up-table (lut) logic and rom applica- tions, the channel memory blocks can be initialized with a given set of data when the device is configured at power up. for lut and rom applications, the user cannot write to memory blocks. channel memory routing interface similar to lbc outputs, the channel memory blocks feature dedicated tracks in the horizontal and vertical routing channels for the data outputs and the flag outputs, as shown in figure 6 . this allows the channel memory blocks to be expanded easily. these dedicated lines can be routed to i/o pins as chip outputs or to other logic block clusters to be used in logic equations. table 2. arbitration result: address match signal becomes active port a port b result of arbitration comment read read no arbitration required both ports read at the same time write read port a gets priority if port b requests first then it will read the current data. the output will then change to the newly written data by port a read write port b gets priority if port a requests first then it will read the current data. the output will then change to the newly written data by port b write write port a gets priority port b is blocked until port a is finished writing
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 9 of 86 i/o banks the delta39k interfaces the horizontal and vertical routing channels to the pins through i/o banks. there are eight i/o banks per device as shown in figure 7 , and all i/os from an i/o bank are located in the same section of a package for pcb layout convenience. delta39k devices support true vertical migration? (i.e., for each package type, delta39k devices of different densities keep given pins in the same i/o banks). this allows for easy and simple implementation of multiple i/o standards during the design and prototyping phase, before a final density has been determined. please refer to the application note titled ?family, package and density migration in delta 39k and quantum38k cplds.? each i/o bank contains several i/o cells, and each i/o cell contains an input/output register, an output enable register, programmable slew rate control and programmable bus hold control logic. each i/o cell drives a pin output of the device; the cell also supplies an input to the device that connects to a dedicated track in the associated routing channel. each i/o bank can use any supported i/o standard by supplying appropriate v ref and v ccio voltages and config- uring the i/o through the warp software. all the v ref and v ccio pins in an i/o bank must be connected to the same v ref and v ccio voltage respectively. this requirement restricts the number of i/o standards supported by an i/o bank at any given time. the number of i/os which can be used in each i/o bank depend on the type of i/o standards and the number of v ccio and gnd pins being used. this restriction is derived from the electromigration limit of the v ccio and gnd bussing on the chip. please refer to the note on page 17 and the application note titled ?delta39k family device i/o standards and config- urations? for details. i/o cell figure 8 is a block diagram of the delta39k i/o cell. the i/o cell contains a three-state input buffer, an output buffer, and a register that can be configured as an input or output register. the output buffer has a slew rate control option that can be used to configure the output for a slower slew rate. the input of the device and the pin output can each be configured as registered or combinatorial; however, only one path can be configured as registered in a given design. the output enable in an i/o cell can be selected from one of the four global control signals or from one of two output control channel (occ) signals. the output enable can be configured as always enabled or always disabled or it can be controlled by one of the remaining inputs to the mux. the selection is done via a mux that includes v cc and gnd as inputs. figure 6. block diagram of channel memory block 4096-bit dual-port array configurable as async/sync dual-port or sync fifo configurable as 4k x 1, 2k x 2, 1k x 4, and 512 x 8 block sizes horizontal channel all channel memory inputs are driven from the routing channels all channel memory outputs drive dedicated tracks in the routing channels gclk[3:0] global cloc k signals vertical channel delta39k bank 0 bank 1 bank 4 bank 5 bank 2 bank 3 bank 6 bank 7 delta39k figure 7. delta39k i/o bank block diagram
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 10 of 86 i/o signals there are four dedicated inputs (gctl[3:0]) that are used as global i/o control signals available to every i/o cell. these global i/o control signals may be used as output enables, register resets and register clock enables as shown in figure 8 . these global control signals, driven from four dedicated pins, can only be used as active-high signals and are available only to the i/o cells thereby implementing fast resets, register and output enables. in addition, there are six occ signals available to each i/o cell. these control signals may be used as output enables, register resets and register clock enables as shown in figure 8 . unlike global control signals, these occ signal can be driven from internal logic or and i/o pin. one of the four global clocks can be selected as the clock for the i/o cell register. the clock mux output is an input to a clock polarity mux that allows the input/output register to be clocked on either edge of the clock slew rate control the output buffer has a slew rate control option. this allows the output buffer to slew at a fast rate (3 v/ns) or a slow rate (1 v/ns). all i/os default to fast slew rate. for designs concerned with meeting fcc emissions standards the slow edge provides for lower system noise. for designs requiring very high performance the fast edge rate provides maximum system performance. dq res e global i/o control signals output control channel occ global clock signals slew rate control c i/o from output pim to routing channel oe mux register input mux register enable mux output mux clock mux clock polarity mux register reset mux input mux bus hold c dq res c registered oe mux c c c 3 c 3 c 2 3 c c c figure 8. block diagram of i/o cell table 3. i/o standards i/o standard v ref (v) v ccio termination voltage (v tt ) min. max. lvttl n/a 3.3v n/a lvcmos 3.3v n/a lvcmos3 3.0v n/a lvcmos2 2.5v n/a lvcmos18 1.8v n/a 3.3v pci 3.3v n/a gtl+ 0.9 1.1 n/a 1.5 sstl3 i 1.3 1.7 3.3v 1.5 sstl3 ii 1.3 1.7 3.3v 1.5 sstl2 i 1.15 1.35 2.5v 1.25 sstl2 ii 1.15 1.35 2.5v 1.25 hstl i 0.68 0.9 1.5v 0.75 hstl ii 0.68 0.9 1.5v 0.75 hstl iii 0.68 0.9 1.5v 1.5 hstl iv 0.68 0.9 1.5v 1.5
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 11 of 86 programmable bus hold on each i/o pin, user-programmable-bus-hold is included. bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device?s performance. as a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in bus- interface applications. bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to v cc or gnd. for more information, see the application note titled ?understanding bus-hold?a feature of cypress cplds.? clocks delta39k has four dedicated clock input pins (gclk[3:0]) to accept system clocks. one of these clocks (gclk[0]) may be selected to drive an on-chip phase-locked loop (pll) for frequency modulation (see figure 9 for details). the global clock tree for a delta39k device can be driven by a combination of the dedicated clock pins and/or the pll- derived clocks. the global clock tree consists of four global clocks that go to every macrocell, memory block, and i/o cell. clock tree distribution the global clock tree performs two primary functions. first, the clock tree generates the four global clocks by multiplexing four dedicated clocks from the package pins and four pll driven clocks. second, the clock tree distributes the four global clocks to every cluster, channel memory, and i/o block on the die. the global clock tree is designed such that the clock skew is minimized while maintaining an acceptable clock delay. spread aware pll each device in the delta39k family features an on-chip pll designed using spread aware technology for low emi applica- tions. in general, plls are used to implement time-division- multiplex circuits to achieve higher performance with fewer device resources. for example, a system that operates on a 32-bit data path that runs at 40 mhz can be implemented with 16-bit circuitry that runs internally at 80 mhz. plls can also be used to take advantage of the positioning of the internally generated clock edges to shift performance towards improved setup, hold or clock-to-out times. there are several frequency multiply (x1, x2, x3, x4, x5, x6, x8, x16) and divide (/1, /2, /3, /4, /5, /6, /8, /16) options available to create a wide range of clock frequencies from a single clock input (gclk[0]). for increased flexibility, there are seven phase shifting options which allow clock skew/deskew by 45, 90, 135, 180, 225, 270, or 315. the spread aware feature refers to the ability of the pll to track a spread-spectrum input clock such that its spread is seen on the output clock with the pll staying locked. the total amount of spread on the input clock should be limited to 0.6% of the fundamental frequency. spread aware feature is supported only with x1, x2, and x4 multiply options. the voltage controlled oscillator (vco), the core of the delta39k pll is designed to operate within the frequency range of 100 mhz to 266 mhz. hence, the multiply option combined with input (gclk[0]) frequency should be selected such that this vco operating frequency requirement is met. this is demonstrated in table 4 (columns 1, 2, and 3). another feature of this pll is the ability to drive the output clock (intclk) off the delta39k chip to clock other devices on the board, as shown in figure 9 above. this off-chip clock is half the frequency of the output clock as it has to go through a register (i/o register or a macrocell register). this pll can also be used for board de-skewing purpose by driving a pll output clock off-chip, routing it to the other devices on the board and feeding it back to the pll?s external feedback input (gclk[1]). when this feature is used, only limited multiply, divide and phase shift options can be used. table 4 describes the valid multiply and divide options that can be used without external feedback. table 5 describes the valid multiply and divide options that can be used with an external feedback. g clk[3:0] gclk0 gclk1 fb source clock clock tree delay lock pll x1, x2, x3, x4, 5x, x6, x8, x16 gclk0 gclk1 gclk2 intclk 0 intclk1 intclk2 normal i/o signal path lock detect/io pin any register (tff) intclk0, intclk1, intclk2, intclk3 send a global clock off chip c c c c c c clk 0 0 clk 90 0 clk 180 0 clk 270 0 clk 225 0 clk 135 0 clk 45 0 clk 315 0 divide gclk3 intclk3 2 2 2 2 2 fb off-chip signal (external feedback) phase selection phase selection phase selection phase selection ? 1-6,8,16 divide ? 1-6,8,16 divide ? 1-6,8,16 divide ? 1-6,8,16 figure 9. block diagram of spread aware pll
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 12 of 86 table 6 describes the valid phase shift options that can be used with or without an external feedback. table 7 is an example of the effect of all the available divide and phase shift options on a vco output of 250 mhz. it also shows the effect of division on the duty cycle of the resultant clock. note that the duty cycle is 50-50 when a vco output is divided by an even number. also note that the phase shift applies to the vco output and not to the divided output. for more details on the architecture and operation of this pll please refer to the application note entitled ?delta39k pll and clock tree?. table 4. valid pll multiply and divide options?without external feedback input frequency (gclk[0]) f plli (mhz) valid multiply options valid divide options value vco output frequency (mhz) value output frequency (intclk[3:0]) f pllo (mhz) off-chip clock frequency dc?12.5 n/a n/a n/a dc?12.5 dc?6.25 100?133 1 100?133 1?6, 8, 16 6.25?133 3.125?66 50?133 2 100?266 1?6, 8, 16 6.25?266 3.125?133 33.3?88.7 3 100?266 1?6, 8, 16 6.25?266 3.1?266 25?66 4 100?266 1?6, 8, 16 6.25?266 3.125?133 20?53.2 5 100?266 1?6, 8, 16 6.25?266 3.1?133 16.6?44.3 6 100?266 1?6, 8, 16 6.25?266 3.1?133 12.5?33 8 100?266 1?6, 8, 16 6.25?266 3.125?133 12.5?16.625 16 200?266 1?6, 8, 16 6.25?266 3.125?133 table 5. valid pll multiply and divide options?with external feedback input (gclk) frequency f plli (mhz) valid multiply options valid divide options value vco output frequency (mhz) value output (intclk) frequency f pllo (mhz) off-chip clock frequency 50?133 1 100?266 1 100?266 50?133 25?66.5 1 100?266 2 50?133 25?66.5 16.67?44.33 1 100?266 3 33.33?88.66 16.67?44.33 12.5?33.25 1 100?266 4 25?66.5 12.5?33.25 12.5?26.6 1 125?266 5 25?53.2 12.5?26.6 12.5?22.17 1 150?266 6 25?44.34 12.5?22.17 12.5?16.63 1 200?266 8 25?33.25 12.5?16.63 table 6. recommended pll phase shift options without external feedback with external feedback 0,45, 90, 135, 180, 225, 270, 315 0 table 7. timing of clock phases for all divide options for a v co output frequency of 250 mhz divide factor period (ns) duty cycle% 0 (ns) 45 (ns) 90 (ns) 135 (ns) 180 (ns) 225 (ns) 270 (ns) 315 (ns) 1 4 40?60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2 8 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3 12 33?67 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4 16 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5 20 40?60 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 6 24 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 8 32 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 16 64 50 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 13 of 86 compactpci hot swap the compactpci hot swap specification allows the removal and insertion of cards into compactpci sockets without switching-off the bus. delta39k cplds can be used as a compactpci host or target on these cards. this feature is useful in telecommunication and networking applications as it allows implementation of high availability systems, where repairs and upgrades can be done without downtime. delta39k cplds are compactpci hot swap ready per compactpci hot swap specification r2.0, with the following exception: the i/o cells do not provide bias voltage support. external resistors can be used to achieve this, per section 3.1.3.1 of the compactpci hot swap specification r2.0. a simple board level solution is provided in the application note titled ?hot-swapping delta39k and quantum38k cplds.? timing model one important feature of the delta39k family is the simplicity of its timing. all combinatorial and registered/synchronous delays are worst case and system performance is static (as shown in the ac specs section) as long as data is routed through the same horizontal and vertical channels. figure 10 illustrates the true timing model for the 200-mhz devices. for synchronous clocking of macrocells, a delay is incurred from macrocell clock to macrocell clock of separate logic blocks within the same cluster, as well as separate logic blocks within different clusters. this is respectively shown as t scs and t scs2 in figure 10. for combinatorial paths, any input to any output (from corner to corner on the device), incurs a worst- case delay in the 39k100 regardless of the amount of logic or which horizontal and vertical channels are used. this is the t pd shown in figure 10. for synchronous systems, the input set- up time to the output macrocell register and the clock to output time are shown as the parameters t mcs and t mcco shown in the figure 10. these measurements are for any output and synchronous clock, regardless of the logic placement. the delta39k features: no dedicated vs. i/o pin delays no penalty for using 0 ? 16 product terms no added delay for steering product terms no added delay for sharing product terms no output bypass delays. the simple timing model of the delta39k family eliminates unexpected performance penalties. family, package, and density migration in delta39k cplds the delta39k cplds combine dense logic, embedded mem- ory and configurable i/o standards. further design flexibility is added by the easy migration options available between differ- ent packages and densities of delta39k cpld offerings. this migration flexibility makes changes or additions to designs simple even after pcb layout. it also provides the ability for experimental designs to be used on production pcbs. please refer to the application note titled ?family, package, and density migration in delta39k cplds.?
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 14 of 86 ieee 1149.1-compliant jtag operation the delta39k family has an ieee 1149.1 jtag interface for both boundary scan and isr operations. four dedicated pins are reserved on each device for use by the test access port (tap). boundary scan the delta39k family supports bypass, sample/preload, extest, intest, idcode and usercode boundary scan instruc- tions. the jtag interface is shown in figure 11 . in-system reprogramming (isr) in-system reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. this combination means design changes during debug or field upgrades do not cause board respins. the delta39k family implements isr by providing a jtag compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance. configuration each device of the delta39k family is available in a volatile and a self-boot package. cypress?s cpld boot eeprom is used to store configuration data for the volatile solution and an embedded on-chip flash memory device is used for the self- boot solution. for volatile delta39k packages, programming is defined as the loading of a user?s design into the external cpld boot eeprom. for self-boot delta39k packages, programming is defined as the loading of a user?s design into the on-chip flash internal to the delta39k package. configuration is defined as the loading of a user?s design into the delta39k die. channel ram 4 gclk[3:0] lb 0 pim ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim 8 kb sram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 8 kb sram channel ram 4 gclk[3:0] lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram 4 lb 0 pim ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 gclk[3:0] lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram 4 lb 0 pim cluster ram lb 5 lb 4 lb 6 lb 7 lb 2 lb 3 lb 1 cluster ram channel ram channel ram cluster cluster cluster t mcs t pd t scs t mcco t scs2 figure 10. timing model for 39k100 device
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 15 of 86 configuration can begin in two ways. it can be initiated by toggling the reconfig pin from low to high, or by issuing the appropriate ieee std 1149.1 jtag instruction to the delta39k device via the jtag interface. there are two ieee std 1149.1 jtag instructions that initiate configuration of the delta39k. the self config instruction causes the delta39k to (re)configure with data stored in the serial boot prom or the embedded flash memory. the load config instruction causes the delta39k to (re)configure according to data provided by other sources such as a pc, automatic test equipment (ate), or an embedded micro-controller/processor via the jtag interface. for more information on configuring delta39k devices, refer to the application note titled ?config- uring delta39k/quantum38k? at http://www.cypress.com. there are two configuration options available for issuing the ieee std 1149.1 jtag instructions to the delta39k. the first method is to use a pc with the c3isr programming cable and software. with this method, the isr pins of the delta39k devices in the system are routed to a connector at the edge of the printed circuit board. the c3isr programming cable is then connected between the pc and this connector. a simple configuration file instructs the isr software of the programming operations to be performed on the delta39k devices in the system. the isr software then automatically completes all of the necessary data manipulations required to accomplish configuration, reading, verifying, and other isr functions. for more information on the cypress isr interface, see the isr programming kit data sheet (cy3900i). the second configuration option for the delta39k is to utilize the embedded controller or processor that already exists in the system. the delta39k isr software assists in this method by converting the device hex file into the isr serial stream that contains the isr instruction information and the addresses and data of locations to be configured. the embedded controller then simply directs this isr stream to the chain of delta39k devices to complete the desired reconfiguration or diagnostic operations. contact your local sales office for infor- mation on the availability of this option. programming the on-chip flash device of the delta39k self-boot package is programmed by issuing the appropriate ieee std 1149.1 jtag instruction to the internal flash memory via the jtag interface. this can be done automatically using isr/stapl software. the configuration bits are sent from a pc through the jtag port into the delta39k via the c3isr programming cable. the data is then internally passed from delta39k to the on-chip flash. for more information on how to program the delta39k through isr/stapl, please refer to the isr/stapl user guide. the external cpld boot eeprom used to store configuration data for the delta39k volatile package is programmed through cypress?s cydh2200e cpld boot prom programming kit via a two-wire interface. for more information on how to program the cpld boot eeprom, please refer to the data sheet titled ? cydh2200e cpld boot prom programming kit .? for more information on the architecture and timing speci- fication of the boot eeprom, refer to the data sheet titled ? 512k/1mb cpld boot eeprom ? or ? 2-mbit cpld boot eeprom. ? third-party programmers cypress support is available on a wide variety of third-party programmers. all major programmers (including bp micro, system general, hi-lo) support the delta39k family. development software support warp warp is a state-of-the-art design environment for designing with cypress programmable logic. warp utilizes a subset of ieee 1076/1164 vhdl and ieee 1364 as the hardware description language (hdl) for design entry. warp accepts vhdl or verilog input, synthesizes and optimizes the entered design, and outputs a configuration bitstream for the desired delta39k device. for simulation, warp provides a graphical waveform simulator as well as vhdl and verilog timing models. vhdl and verilog are open, powerful, non-proprietary hardware description languages (hdls) that are standards for behavioral design entry and simulation. hdl allows designers to learn a single language that is useful for all facets of the design process. third-party software cypress products are supported in a number of third-party design entry and simulation tools. refer to the third-party software data sheet or contact your local sales office for a list of currently supported third party vendors. instruction register boundary scan idcode usercode isr prog. bypass reg. data registers jtag tap controller td o tdi tms tclk figure 11. jtag interface
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 16 of 86 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature (39k200, 208 eqfp) ................................. ?45 c to +125 c storage temperature (all other densities and packages) .............. ?65 c to +150 c soldering temperature................................................. 220 c ambient temperature with power applied............................................... ?40 c to +85 c junction temperature...................................................135c v cc to ground potential...................................?0.5v to 4.6v v ccio to ground potential................................?0.5v to 4.6v dc voltage applied to outputs in high-z state ..................................................?0.5v to 4.5v dc input voltage...............................................?0.5v to 4.5v dc current into outputs........................................ 20 ma [6] static discharge voltage (per jedec eia./jesd22?a114a)............................ >2001v latch-up current ..................................................... >200 ma note: 6. dc current into outputs is 36 ma with hstl iii, 48 ma with hstl iv, and 36 ma with gtl+ (with 25w pull-up resistor and v tt = 1.5). 7. input leakage current is 10 a for all the pins on all the delta39k package except the following pins in delta39k100 packages: the input leakage current spe c for these pins in 200 a 8. not more than one output should be tested at a time. duration of the short circuit should not exceed 1 second. v out = 0.5v has been chosen to avoid test problems caused by tester-ground degradation. tested initially and after any design or process changes that may affect these pa rameters. operating range range ambient temperature junction temperature output condition v ccio v cc v ccjtag / v cccnfg v ccpll v ccprg commercial 0 c to +70 c 0 c to +85 c 3.3v 3.3v 0.3v 3.3v 0.3v or 2.5v 0.2v (39kv) same as v ccio same as v cc 3.3v 0.3v 2.5v 2.5v 0.2v 1.8v 1.8v 0.15v 1.5v 1.5v 0.1v [5] industrial ?40 c to +85c ?40 c to +100c 3.3v 3.3v 0.3v 2.5v 2.5v 0.2v 1.8v 1.8v 0.15v 1.5v 1.5v 0.1v [5] dc characteristics parameter description test conditions v ccio = 3.3v v ccio = 2.5v v ccio = 1.8v unit min. max. min. max. min. max. v drint data retention v cc voltage (config data may be lost below this) 1.5 1.5 1.5 v v drio data retention v ccio voltage (config data may be lost below this) 1.2 1.2 1.2 v i ix [7] input leakage current gnd v i 3.6v ?10 10 ?10 10 ?10 10 a i oz output leakage current gnd v o v ccio ?10 10 ?10 10 ?10 10 a i os [8] output short circuit current v ccio = max. v out = 0.5v ?160 ?160 ?160 a i bhl input bus hold low sustaining current v cc = min. v pin = v il +40 +30 +25 a i bhh input bus hold high sustaining current v cc = min. v pin = v ih ?40 ?30 ?25 a i bhlo input bus hold low overdrive current v cc = max. +250 +200 +150 a i bhho input bus hold high overdrive current v cc = max. ?250 ?200 ?150 a i cc0 standby current 39k30 39k50 39k100 39k165 39k200 all bins 20 20 30 60 60 all bins 20 20 30 60 60 ?125 bin 3 3 5 10 10 ?83 bin 12 12 20 40 40 a delta39k100 package pins 388-bga b4, c2 484-fbga b8, g9 676-fbga f11, j11
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 17 of 86 power-up sequence requirements upon power-up, all the outputs remain three-stated until all the v cc pins have powered-up to the nominal voltage and the part has completed configuration. the part will not start configuration until v cc , v ccio , v ccjtag , v cccnfg , v ccpll and v ccprg have reached nominal voltage. v cc pins can be powered up in any order. this includes v cc , v ccio , v ccjtag , v cccnfg , v ccpll and v ccprg . all v ccio s on a bank should be tied to the same potential and powered up together. all v ccio s (even the unused banks) need to be powered up to at least 1.5v before configuration has completed. maximum ramp time for all v cc s should be 0v to nominal voltage in 100 ms. notes: 9. pci spec (rev 2.2) requires the idsel pin to have capacitance less than or equal to 8 pf. delta39k pin tables starting from p age 45, identify all the i/o pins in a given package, which can be used as idsel in a pci design. all other i/o pins meet the pci requirement of capacitance less th an or equal to 10 pf. 10. the number of i/os which can be used in each i/o bank depends on the type of i/o standards and the number of v ccio and gnd pins being used. please refer to the application note titled ?delta39k and quantum38k i/o standards and configurations? for details. the source current limit per i/o bank per vccio pin is 165 ma. the sink current limit per i/o bank per gnd pin is 230 ma. 11. see ?power-up sequence requirements? below for v ccio requirement. 12. 25w resistor terminated to termination voltage of 1.5v. capacitance parameter description test conditions min. max. unit c i/o input/output capacitance v in = v ccio @ f = 1 mhz 25c 10 pf c clk clock signal capacitance v in = v ccio @ f = 1 mhz 25c 5 12 pf c pci pci-compliant [9] capacitance v in = v ccio @ f = 1 mhz 25c 8 pf dc characteristics (i/o) [10] i/o standards v ref (v) v ccio (v) v oh (v) v ol (v) v ih (v) v il (v) @ i oh =v oh (min.) @ i ol = v ol (max.) min. max. min. max. lvttl ?2 ma n/a 3.3 ?2 ma 2.4 2 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvttl ?4 ma 3.3 ?4 ma 2.4 4 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvttl ?6 ma 3.3 ?6 ma 2.4 6 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvttl ?8 ma 3.3 ?8 ma 2.4 8 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvttl ?12 ma 3.3 ?12 ma 2.4 12 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvttl ?16 ma 3.3 ?16 ma 2.4 16 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvttl ?24 ma 3.3 ?24 ma 2.4 24 ma 0.4 2.0v v ccio + 0.3 ?0.3v 0.8v lvcmos 3.3 ?0.1 ma v ccio ? 0.2v 0.1 ma 0.2 2.0v v ccio + 0.3 ?0.3v 0.8v lvcmos3 3.0 ?0.1 ma v ccio ? 0.2v 0.1 ma 0.2 2.0v v ccio + 0.3 ?0.3v 0.8v lvcmos2 2.5 ?0.1 ma 2.1 0.1 ma 0.2 1.7v v ccio + 0.3 ?0.3v 0.7v ?1.0 ma 2.0 1.0 ma 0.4 ?2.0 ma 1.7 2.0 ma 0.7 lvcmos18 1.8 ?2 ma v ccio ? 0.45v 2.0 ma 0.45 0.65v ccio v ccio + 0.3 ?0.3v 0.35v ccio 3.3v pci 3.3 ?0.5 ma 0.9v ccio 1.5 ma 0.1v ccio 0.5v ccio v ccio + 0.5 ?0.5v 0.3v ccio gtl+ 1.0 [11] 36 ma [12] 0.6 v ref + 0.2 v ref ? 0.2 sstl3 i 1.5 3.3 ?8 ma v ccio ? 1.1v 8 ma 0.7 v ref + 0.2 v ccio + 0.3 ?0.3v v ref ? 0.2 sstl3 ii 1.5 3.3 ?16 ma v ccio ? 0.9v 16 ma 0.5 v ref + 0.2 v ccio + 0.3 ?0.3v v ref ? 0.2 sstl2 i 1.25 2.5 ?7.6 ma v ccio ? 0.62v 7.6 ma 0.54 v ref + 0.18 v ccio + 0.3 ?0.3v v ref ? 0.18 sstl2 ii 1.25 2.5 ?15.2 ma v ccio ? 0.43v 15.2 ma 0.35 v ref + 0.18 v ccio + 0.3 ?0.3v v ref ? 0.18 hstl i 0.75 1.5 ?8 ma v ccio ? 0.4v 8 ma 0.4 v ref + 0.1 v ccio + 0.3 ?0.3v v ref ? 0.1 hstl ii 0.75 1.5 ?16 ma v ccio ? 0.4v 16 ma 0.4 v ref + 0.1 v ccio + 0.3 ?0.3v v ref ? 0.1 hstl iii 0.9 1.5 ?8 ma v ccio ? 0.4v 24 ma 0.4 v ref + 0.1 v ccio + 0.3 ?0.3v v ref ? 0.1 hstl iv 0.9 1.5 ?8 ma v ccio ? 0.4v 48 ma 0.4 v ref + 0.1 v ccio + 0.3 ?0.3v v ref ? 0.1 configuration parameters parameter description min. unit t reconfig reconfig pin low time before it goes high 200 ns
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 18 of 86 switching characteristics ? parameter descriptions over the operating range [13] parameter description combinatorial mode parameters t pd delay from any pin input, through any cluster on the channel associated with that pin input, to any pin output on the horizontal or vertical channel associated with that cluster t ea global control to output enable t er global control to output disable t prr asynchronous macrocell reset or preset recovery time from any pin input on the horizontal or vertical channel associated with the cluster the macrocell is in t pro asynchronous macrocell reset or preset from any pin input on the horizontal or vertical channel associated with the cluster that the macrocell is in to any pin output on those same channels t prw asynchronous macrocell reset or preset minimum pulse width, from any pin input to a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated with synchronous clocking parameters t mcs set-up time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock t mch hold time of any input pin to a macrocell in any cluster on the channel associated with that input pin, relative to a global clock t mcco global clock to output of any macrocell to any output pin on the horizontal or vertical channel associated with the cluster that macrocell is in t ios set-up time of any input pin to the i/o cell register associated with that pin, relative to a global clock t ioh hold time of any input pin to the i/o cell register associated with that pin, relative to a global clock t ioco clock to output of an i/o cell register to the output pin associated with that register t scs macrocell clock to macrocell clock through array logic within the same cluster t scs2 macrocell clock to macrocell clock through array logic in different clusters on the same channel t ics i/o register clock to any macrocell clock in a cluster on the channel the i/o register is associated with t ocs macrocell clock to any i/o register clock on the horizontal or vertical channel associated with the cluster that the macrocell is in t chz clock to output disable (high-impedance) t clz clock to output enable (low-impedance) f max maximum frequency with internal feedback?within the same cluster f max2 maximum frequency with internal feedback?within different clusters at the opposite ends of a horizontal or vertical channel product term clock t mcspt set-up time for macrocell used as input register, from input to product term clock t mchpt hold time of macrocell used as an input register t mccopt product term clock to output delay from input pin t scs2pt register to register delay through array logic in different clusters on the same channel using a product term clock channel interconnect parameters t chsw adder for a signal to switch from a horizontal to vertical channel and vice-versa t cl2cl cluster-to-cluster delay adder (through channels and channel pim) miscellaneous delays t cpld delay from the input of a cluster pim, through a macrocell in the cluster, back to a cluster pim input. this parameter can be added to the t pd and t scs parameters for each extra pass through the and/or array required by a given signal path t mccd adder for carry chain logic per macrocell t iod delay from the input of the output buffer to the i/o pin t ioin delay from the i/o pin to the input of the channel buffer note: 13. add t chsw to signals making a horizontal to vertical channel switch or vice-versa.
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 19 of 86 t ckin delay from the clock pin to the input of the clock driver t ioregpin delay from the i/o pin to the input of the i/o register pll parameters t mccj maximum cycle to cycle jitter time t dwsa pll zero phase delay with clock tree deskewed t dwosa pll zero phase delay without clock tree deskewed t lock lock time for the pll t induty input duty cycle f plli input frequency of the pll f pllo output frequency of the pll f pllvco pll vco frequency of operation p saplli percentage modulation allowed (spread awareness) on the pll input clock f mplli frequency of modulation allowed on pll input clock. this specifies how fast the f plli sweeps between f plli * (1?p saplli /100) and f plli * (1+ p saplli /100) jtag parameters t jckh tclk high time t jckl tclk low time t jcp tclk clock period t jsu jtag port set-up time (tdi/tms inputs) t jh jtag port hold time (tdi/tms inputs) t jco jtag port clock to output time (tdo) t jxz jtag port valid output to high impedance (tdo) t jzx jtag port high impedance to valid output (tdo) switching characteristics ? parameter descriptions over the operating range [13] (continued) parameter description cluster memory timing parameter descriptions over the operating range parameter description asynchronous mode parameters t clmaa cluster memory access time. delay from address change to read data out t clmpwe write enable pulse width t clmsa address set-up to the beginning of write enable with both signals from the same i/o block t clmha address hold after the end of write enable with both signals from the same i/o block t clmsd data set-up to the end of write enable t clmhd data hold after the end of write enable synchronous mode parameters t clmcyc1 clock cycle time for flow through read and write operations (from macrocell register through cluster memory back to a macrocell register in the same cluster) t clmcyc2 clock cycle time for pipelined read and write operations (from cluster memory input register through the memory to cluster memory output register) t clms address, data, and we set-up time of pin inputs, relative to a global clock t clmh address, data, and we hold time of pin inputs, relative to a global clock t clmdv1 global clock to data valid on output pins for flow through data t clmdv2 global clock to data valid on output pins for pipelined data t clmmacs1 cluster memory input clock to macrocell clock in the same cluster t clmmacs2 cluster memory output clock to macrocell clock in the same cluster t macclms1 macrocell clock to cluster memory input clock in the same cluster
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 20 of 86 t macclms2 macrocell clock to cluster memory output clock in the same cluster internal parameters t clmclaa asynchronous cluster memory access time from input of cluster memory to output of cluster memory channel memory timing parameter descriptions over the operating range parameter description dual port asynchronous mode parameters t chmaa channel memory access time. delay from address change to read data out t chmpwe write enable pulse width t chmsa address set-up to the beginning of write enable with both signals from the same i/o block t chmha address hold after the end of write enable with both signals from the same i/o block t chmsd data set-up to the end of write enable t chmhd data hold after the end of write enable t chmba channel memory asynchronous dual port address match (busy access time) dual port synchronous mode parameters t chmcyc1 clock cycle time for flow through read and write operations (from macrocell register through channel memory back to a macrocell register in the same cluster) t chmcyc2 clock cycle time for pipelined read and write operations (from channel memory input register through the memory to channel memory output register) t chms address, data, and we set-up time of pin inputs, relative to a global clock t chmh address, data, and we hold time of pin inputs, relative to a global clock t chmdv1 global clock to data valid on output pins for flow through data t chmdv2 global clock to data valid on output pins for pipelined data. t chmbdv channel memory synchronous dual-port address match (busy, clock to data valid) t chmmacs1 channel memory input clock to macrocell clock in the same cluster t chmmacs2 channel memory output clock to macrocell clock in the same cluster t macchms1 macrocell clock to channel memory input clock in the same cluster t macchms2 macrocell clock to channel memory output clock in the same cluster synchronous fifo data parameters t chmclk read and write minimum clock cycle time t chmfs data, read enable, and write enable set-up time relative to pin inputs t chmfh data, read enable, and write enable hold time relative to pin inputs t chmfrdv data access time to output pins from rising edge of read clock (read clock to data valid) t chmmacs channel memory fifo read clock to macrocell clock for read data t macchms macrocell clock to channel memory fifo write clock for write data synchronous fifo flag parameters t chmfo read or write clock to respective flag output at output pins t chmmacf read or write clock to macrocell clock with fifo flag t chmfrs master reset pulse width t chmfrsr master reset recovery time t chmfrsf master reset to flag and data output time t chmskew1 read/write clock skew time for full flag t chmskew2 read/write clock skew time for empty flag t chmskew3 read/write clock skew time for boundary flags cluster memory timing parameter descriptions over the operating range (continued) parameter description
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 21 of 86 internal parameters t chmchaa asynchronous channel memory access time from input of channel memory to output of channel memory channel memory timing parameter descriptions over the operating range (continued) parameter description switching characteristics ? parameter values over the operating range parameter 233 200 181 125 83 unit min. max. min. max. min. max. min. max. min. max. combinatorial mode parameters t pd 7.2 7.5 8.5 10 15 ns t ea 4.5 5.0 5.6 9.0 10 ns t er 4.5 5.0 5.3 9.0 10 ns t prr 6.0 6.0 6.0 8.0 10 ns t pro 9.5 10 10.5 13 15 ns t prw 3.3 3.6 4.0 6.0 7.0 ns synchronous clocking parameters t mcs 2.7 3.0 3.5 5.0 6.7 ns t mch 000 0 0 ns t mcco 5.8 6.0 7.0 10 12 ns t ios 1.0 1.0 1.2 2.0 2.5 ns t ioh 0.9 1.0 1.2 2.0 2.5 ns t ioco 3.8 4.0 4.5 7.0 8.0 ns t scs 3.4 3.5 3.6 6.4 9.6 ns t scs2 4.3 4.5 5.5 8.0 12 ns t ics 4.5 5.0 5.5 8.0 12 ns t ocs 4.5 5.0 5.5 8.0 12 ns t chz 3.5 3.5 3.8 6.0 7.0 ns t clz 1.5 1.5 1.5 1.5 1.5 ns f max 294 286 278 156 104 mhz f max2 233 222 181 125 83 mhz product term clocking parameters t mcspt 2.7 3.0 3.3 5.0 6.0 ns t mchpt 0.9 1.0 1.4 2.0 2.5 ns t mccopt 7.5 8.0 8.8 11.0 15.0 ns t scs2pt 6.0 6.5 7.2 10.0 15.0 ns channel interconnect parameters t chsw 0.9 1.0 1.2 1.7 2.0 ns t cl2cl 1.8 2.0 2.3 2.8 3.0 ns miscellaneous parameters t cpld 2.8 3.0 3.3 4.0 5.0 ns t mccd 0.22 0.25 0.28 0.35 0.38 ns pll parameters t mccj ?150 150 ?150 150 ?150 150 ?180 180 ?200 200 ps t dwsa ?1.35 ?0.85 ?1.35 ?0.85 ?1.35 ?0.85 ?2.0 ?1.5 ?2.9 ?2.4 ns t dwosa ?150 150 ?150 150 ?150 150 ?180 180 ?200 200 ps t lock 250 250 250 250 250 ms
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 22 of 86 input and output standard timing delay adjustments all the timing specifications in this data sheet are specified based on lvcmos compliant inputs and outputs (fast slew rates). [15] apply following adjustments if the inputs and outputs are configured to operate at other standards. t induty 40 60 40 60 40 60 40 60 40 60 % f pllo [14] 6.2 266 6.2 266 6.2 266 6.2 200 6.2 200 mhz f plli [14] 12.5 133 12.5 133 12.5 133 12.5 100 12.5 100 mhz f pllvco 100 266 100 266 100 266 100 266 100 266 mhz p saplli ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 ?0.3 +0.3 % f mplli 50 50 50 50 50 khz jtag parameters t jckh 25 25 25 25 25 ns t jckl 25 25 25 25 25 ns t jcp 50 50 50 50 50 ns t jsu 10 10 10 10 10 ns t jh 10 10 10 10 10 ns t jco 20 20 20 20 20 ns t jxz 20 20 20 20 20 ns t jzx 20 20 20 20 20 ns switching characteristics ? parameter values over the operating range (continued) parameter 233 200 181 125 83 unit min. max. min. max. min. max. min. max. min. max. i/o standard output delay adjustments input delay adjustments fast slew rate slow slew rate (additional delay to fast slew rate) t iod t ea t er t iodslow t easlow t erslow t ioin t ckin t ioregpin lvttl ? 2 ma 2.75 0 0 2.6 2.0 2.0 0 0 0 lvttl ? 4 ma 1.8 0 0 2.5 2.0 2.0 0 0 0 lvttl ? 6 ma 1.8 0 0 2.5 2.0 2.0 0 0 0 lvttl ? 8 ma 1.2 0 0 2.4 2.0 2.0 0 0 0 lvttl ? 12 ma 0.6 0 0 2.3 2.0 2.0 0 0 0 lvttl ? 16 ma 0.16 0 0 2.0 2.0 2.0 0 0 0 lvttl ? 24 ma 0 0 0 1.6 2.0 2.0 0 0 0 lvcmos 0 0 0 2.0 2.0 2.0 0 0 0 lvcmos3 0.14 0.05 0 2.0 2.0 2.0 0.1 0.1 0.2 lvcmos2 0.41 0.1 0 2.0 2.0 2.0 0.2 0.2 0.4 lvcmos18 1.6 0.7 0.1 2.1 2.0 2.0 0.5 0.4 0.3 3.3v pci ?0.14 0 0 2.0 2.0 2.0 0 0 0 gtl+ 0.02 [16] 0.6 [16] 0.9 [16] 2.0 2.0 2.0 0.5 0.4 0.2 sstl3 i ?0.15 0.3 0.1 2.0 2.0 2.0 0.5 0.3 0.3 sstl3 ii ?0.4 0.2 0 2.0 2.0 2.0 0.5 0.3 0.3 notes: 14. refer to page 11 and the application note titled ?delta39k pll and clock tree? for details on the pll operation. 15. for ?slow slew rate? output delay adjustments, refer to warp software?s static timing analyzer results. 16. these delays are based on falling edge output. the rising edge delay depends on the size of pull-up resistor and termination voltage.
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 23 of 86 sstl2 i ?0.02 0.4 0 2.0 2.0 2.0 0.9 0.5 0.6 sstl2 ii ?0.22 0.2 0 2.0 2.0 2.0 0.9 0.5 0.6 hstl i 0.94 0.9 0.5 2.0 2.0 2.0 0.5 0.5 0.3 hstl ii 0.79 0.8 0.5 2.0 2.0 2.0 0.5 0.5 0.3 hstl iii 0.77 0.5 0.1 2.0 2.0 2.0 0.5 0.5 0.3 hstl iv 0.44 0.6 0 2.0 2.0 2.0 0.5 0.5 0.3 i/o standard output delay adjustments input delay adjustments fast slew rate slow slew rate (additional delay to fast slew rate) t iod t ea t er t iodslow t easlow t erslow t ioin t ckin t ioregpin cluster memory timing parameter values over the operating range parameter 233 200 181 125 83 unit min. max. min. max. min. max. min. max. min. max. asynchronous mode parameters t clmaa 10.2 11 12 17 20 ns t clmpwe 5.5 6 6.5 10 12 ns t clmsa 1.8 2.0 2.2 3.2 4.0 ns t clmha 0.9 1.0 1.1 1.8 2.0 ns t clmsd 5.5 6.0 6.5 10 12 ns t clmhd 0.4 0.5 0.6 0.9 1.0 ns synchronous mode parameters t clmcyc1 9.5 10 10.5 15 20 ns t clmcyc2 5.0 5.0 5.5 8.0 10.0 ns t clms 2.8 3.0 3.8 4.0 5.0 ns t clmh 000 0 0 ns t clmdv1 10 11 12 17 20 ns t clmdv2 7.0 7.5 8.0 10 15 ns t clmmacs1 7.7 8.0 8.5 12 15 ns t clmmacs2 4.5 5.0 5.5 8.0 10 ns t macclms1 3.6 4.0 4.4 6.6 8.0 ns t macclms2 6.0 6.5 7.0 10 12 ns internal parameters t clmclaa 666.5 10 12 ns channel memory timing parameter values over the operating range parameter 233 200 181 125 83 unit min. max. min. max. min. max. min. max. min. max. dual-port asynchronous mode parameters t chmaa 10 11 12 17 20 ns t chmpwe 5.5 6.0 6.5 10 12 ns t chmsa 1.8 2.0 2.2 3.2 4.0 ns t chmha 0.9 1.0 1.1 1.8 2.0 ns t chmsd 5.5 6.0 6.5 10 12 ns t chmhd 0.4 0.5 0.6 0.9 1.0 ns t chmba 8.5 9.0 10.0 14.0 16.0 ns
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 24 of 86 dual-port synchronous mode parameters t chmcyc1 9.5 10 10 15 20 ns t chmcyc2 5.0 5.3 5.4 7.4 10.6 ns t chms 3.0 3.3 3.9 5.0 6.0 ns t chmh 000 0 0 ns t chmdv1 10 11 12 17 20 ns t chmdv2 7.0 7.5 8.0 10 15 ns t chmbdv 8.5 9.0 10.0 14.0 16.0 ns t chmmacs1 8.5 9.0 10.0 14.0 16.0 ns t chmmacs2 4.8 5.0 5.5 8.0 10 ns t macchms1 4.6 5.0 5.4 7.6 9.0 ns t macchms2 7.3 7.3 7.7 10.0 13.0 ns synchronous fifo data parameters t chmclk 4.8 5.0 5.4 7.4 10.6 ns t chmfs 3.7 4.0 4.3 6.0 7.0 ns t chmfh 000 0 0 ns t chmfrdv 6.5 7.0 7.5 10.0 13.0 t chmmacs 4.6 5.0 5.4 7.4 10.6 ns t macchms 4.7 5.0 5.4 7.4 10.6 ns synchronous fifo flag parameters t chmfo 10.5 11 11.5 15 20 ns t chmmacf 8.599.5 13 17 ns t chmfrs 4.5 5.0 5.5 8.0 10 ns t chmfrsr 3.6 4.0 4.4 6.6 8.0 ns t chmfrsf 9.5 10.0 11.0 15.0 18.0 ns t chmskew1 1.8 2.0 2.2 3.2 4.0 ns t chmskew2 1.8 2.0 2.2 3.2 4.0 ns t chmskew3 4.6 5.0 5.4 7.4 10.6 ns internal parameters t chmchaa 6.5 7.0 7.5 10.0 13.0 ns channel memory timing parameter values over the operating range (continued) switching waveforms t pd input combinatorial output combinatorial output
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 25 of 86 switching waveforms (continued) registered output with synchronous clocking (macrocell) t mcs input synchronous t mcco registered output t mch clock registered input in i/o cell t ios data input input register clock t ioco registered output t ioh clock to clock input register clock macrocell register clock t scs t ics pt clock to pt clock data pt clock t scs2pt t mcspt input
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 26 of 86 switching waveforms (continued) asynchronous reset/preset input t pro registered output clock t prr t prw reset/preset output enable/disable global control t er outputs t ea input
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 27 of 86 switching waveforms (continued) cluster memory asynchronous timing address (at read write read write enable t clmpwe input output t clmclaa t clmclaa cluster memory asynchronous timing 2 address (at the read write read write enable t clmpwe input t clmsd t clmhd output t clmsa t clmha t clmaa t clmaa the cluster input) i/o pin)
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 28 of 86 switching waveforms (continued) cluster memory synchronous flow-through timing global address write enable registered input registered output t clms t clms t clms t clmh t clmh t clmh read write read t clmdv1 t clmdv1 t clmdv1 clock t clmcyc1 cluster memory internal clocking macrocell cluster memory input clock cluster memory output clock t clmmacs2 t macclms2 t clmmacs1 t macclms1 input clock
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 29 of 86 switching waveforms (continued) cluster memory output register timing (asynchronous inputs) address t clmcyc2 t clmdv2 write enable input global clock (output register) r egistered o utput cluster memory output register timing (synchronous inputs) address t clmdv2 write enable global clock (output register) registered output (input register) global clock t clmcyc2 t clms t clmh input
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 30 of 86 switching waveforms (continued) channel memory dp asynchronous timing write t chmpwe t chmsa t chmha t chmaa t chmhd address data output t chmaa a n-1 a n a n+1 a n+2 d n d n?1 d n d n+1 t chmsd enable input channel memory internal clocking clock input clock output clock t chmmacs1 t macchms2 t chmmacs2 t macchms1 macrocell input channel memory channel memory
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 31 of 86 switching waveforms (continued) channel memory internal clocking 2 macrocell input clock fifo read clock fifo write clock fifo read or write clock t chmmacs t chmmacf t macchms channel memory dp sram flow-through r/w timing clock t chmcyc1 t chmh t chms write d n+1 t chms t chmh output a n+1 a n+2 a n+3 a n address t chmdv1 t chmdv1 t chmdv1 d n?1 d n+3 d n?1 a n?1 data t chmdv1 d n+3 d n+2 d n+1 d n enable input
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 32 of 86 switching waveforms (continued) channel memory dp sram pipeline r/w timing a n+1 a n+2 d n+1 t chmcyc2 t chmh t chms t chms t chmh a n t chms t chmh a n+3 a n?1 d n+3 d n?1 d n?1 t chmdv2 t chmdv2 d n d n+1 d n+2 t chmdv2 clock write output address data enable input dual-port asynchronous address match busy signal address a a n a n?1 a n a n+1 address t chmba t chmba b n address b match
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 33 of 86 switching waveforms (continued) clock a n a n b n?1 b n+1 t chmbdv a n?1 t chmbdv t chms t chms address b address dual-port synchronous address match busy signal address a match
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 34 of 86 switching waveforms (continued) channel memory synchronous fifo empty/write timing write enable t chmclk t chmfs t chmfh d n+1 registered input empty flag port a clock read enable t chmskew2 t chmfo t chmfo t chmfrdv port b clock re registered output (active low)
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 35 of 86 switching waveforms (continued) channel memory synchronous fifo full/read timing port a clock read enable t chmclk t chmfs registered output full flag port b clock t chmfh t chmskew1 t chmfo t chmfo write enable t chms t chmh t chmfrdv registered input (active low)
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 36 of 86 switching waveforms (continued) channel memory synchronous fifo programmable flag timing t chmclk t chmfs t chmfh port b clock programmable write enable almost empty flag port a clock t chmskew3 t chmfo t chmfo read enable (active low) t chmfs t chmfh t chmclk port b clock programmable write enable almost full flag port a clock t chmskew3 t chmfo t chmfo read enable (active low)
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 37 of 86 switching waveforms (continued) channel memory synchronous fifo master reset timing master reset input read enable / write enable empty/full t chmfrs t chmfrsr t chmfrsf t chmfrsf t chmfrsf half-full/ registered output flags programmable flags almost full programmable almost empty p in count 2 08 = 208 leads 2 56 = 256 balls 3 88 = 388 balls 4 84 = 484 balls 6 76 = 676 balls c y 3 9 1 0 0 v 6 7 6 - 2 0 0 m b c c ypress semiconductor id f amily type 3 9 = delta39k family g ate density 3 0=30k usable gates 165 = 165k usable gates 5 0=50k usable gates 200 = 200k usable gates 1 00=100k usable gates speed 233 = 233 mhz 125 = 125 mhz 200 = 200 mhz 83 = 83 mhz 181 = 181 mhz package type n = plastic quad flat pack (pqfp) nt = thermally enhanced quad flat pack (eqfp) bg = ball grid array (bga) bb = fine-pitch ball grid array (fbga) 1.0-mm lead pitch mg = self-boot solution -- ball grid array mb = self-boot solution -- fine pitch ball grid array 1.0-mm lead pitch operating conditions commercial 0c to +70c industrial --40c to +85c o perating reference voltage v = 3.3v or 2.5v supply voltage z = 1.8v supply voltage
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 38 of 86 delta39k part numbers (ordering information) device speed (mhz) ordering code package name package type self-boot solution operating range 39k30 233 cy39030v208-233ntc nt208 208-lead enhanced quad flat pack commercial cy39030v256-233bbc bb256 256-lead fine pitch ball grid array cy39030v256-233mbc mb256 256-lead fine pitch ball grid array 125 cy39030v208-125ntc nt208 208-lead enhanced quad flat pack cy39030v256-125bbc bb256 256-lead fine pitch ball grid array cy39030v256-125mbc mb256 256-lead fine pitch ball grid array cy39030v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39030v256-125bbi bb256 256-lead fine pitch ball grid array 83 cy39030v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39030v256-83bbc bb256 256-lead fine pitch ball grid array cy39030v256-83mbc mb256 256-lead fine pitch ball grid array cy39030v208-83nti nt208 208-lead plastic quad flat pack industrial cy39030v256-83bbi bb256 256-lead fine pitch ball grid array 39k50 233 cy39050v208-233ntc nt208 208-lead enhanced quad flat pack commercial cy39050v256-233bbc bb256 256-lead fine pitch ball grid array cy39050v388-233mgc mg388 388-lead ball grid array cy39050v484-233mbc mb484 484-lead fine pitch ball grid array 125 cy39050v208-125ntc nt208 208-lead enhanced quad flat pack cy39050v256-125bbc bb256 256-lead fine pitch ball grid array cy39050v388-125mgc mg388 388-lead pitch ball grid array cy39050v484-125mbc mb484 484-lead fine pitch ball grid array 39k50 125 cy39050v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39050v256-125bbi bb256 256-lead fine pitch ball grid array 83 cy39050v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39050v256-83bbc bb256 256-lead fine pitch ball grid array cy39050v388-83mgc mg388 388-lead ball grid array cy39050v484-83mbc mb484 484-lead fine pitch ball grid array cy39050v208-83nti nt208 208-lead plastic quad flat pack industrial cy39050v256-83bbi bb256 256-lead fine pitch ball grid array 39k100 200 cy39100v208b-200ntc nt208 208-lead enhanced quad flat pack commercial cy39100v256b-200bbc bb256 256-lead fine pitch ball grid array cy39100v484b-200bbc bb484 484-lead fine pitch ball grid array cy39100v388b-200mgc mg388 388-lead ball grid array cy39100v676b-200mbc mb676 676-lead fine pitch ball grid array
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 39 of 86 39k100 125 cy39100v208b-125ntc nt208 208-lead enhanced quad flat pack commercial cy39100v256b-125bbc bb256 256-lead fine pitch ball grid array cy39100v484b-125bbc bb484 484-lead fine pitch ball grid array cy39100v388b-125mgc mg388 388-lead ball grid array cy39100v676b-125mbc mb676 676-lead fine pitch ball grid array cy39100v208b-125nti nt208 208-lead enhanced quad flat pack industrial cy39100v256b-125bbi bb256 256-lead fine pitch ball grid array cy39100v484b-125bbi bb484 484-lead fine pitch ball grid array 83 cy39100v208b-83ntc nt208 208-lead enhanced quad flat pack commercial cy39100v256b-83bbc bb256 256-lead fine pitch ball grid array cy39100v484b-83bbc bb484 484-lead fine pitch ball grid array cy39100v388b-83mgc mg388 388-lead ball grid array cy39100v676b-83mbc mb676 676-lead fine pitch ball grid array cy39100v208b-83nti nt208 208-lead enhanced quad flat pack industrial cy39100v256b-83bbi bb256 256-lead fine pitch ball grid array cy39100v484b-83bbi bb484 484-lead fine pitch ball grid array 39k165 181 cy39165v208-181ntc nt208 208-lead enhanced quad flat pack commercial cy39165v484-181bbc bb484 484-lead fine pitch ball grid array cy39165v388-181mgc mg388 388-lead ball grid array cy39165v676-181mbc mb676 676-lead fine pitch ball grid array 125 cy39165v208-125ntc nt208 208-lead enhanced quad flat pack commercial cy39165v484-125bbc bb484 484-lead fine pitch ball grid array cy39165v388-125mgc mg388 388-lead ball grid array cy39165v676-125mbc mb676 676-lead fine pitch ball grid array cy39165v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39165v484-125bbi bb484 484-lead fine pitch ball grid array 83 cy39165v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39165v484-83bbc bb484 484-lead fine pitch ball grid array cy39165v388-83mgc mg388 388-lead ball grid array cy39165v676-83mbc mb676 676-lead fine pitch ball grid array cy39165v208-83nti nt208 208-lead enhanced quad flat pack industrial cy39165v484-83bbi bb484 484-lead fine pitch ball grid array delta39k part numbers (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 40 of 86 note: 17. refer to the data sheets at www.atmel.com for detailed architectural and timing information. 39k200 181 cy39200v208-181ntc nt208 208-lead enhanced quad flat pack commercial cy39200v484-181bbc bb484 484-lead fine pitch ball grid array cy39200v388-181mgc mg388 388-lead ball grid array cy39200v676-181mbc mb676 676-lead fine pitch ball grid array 125 cy39200v208-125ntc nt208 208-lead enhanced quad flat pack commercial cy39200v484-125bbc bb484 484-lead fine pitch ball grid array cy39200v388-125mgc mg388 388-lead ball grid array cy39200v676-125mbc mb676 676-lead fine pitch ball grid array cy39200v208-125nti nt208 208-lead enhanced quad flat pack industrial cy39200v484-125bbi bb484 484-lead fine pitch ball grid array 83 cy39200v208-83ntc nt208 208-lead enhanced quad flat pack commercial cy39200v484-83bbc bb484 484-lead fine pitch ball grid array cy39200v388-83mgc mg388 388-lead ball grid array cy39200v676-83mbc mb676 676-lead fine pitch ball grid array cy39200v208-83nti nt208 208-lead enhanced quad flat pack industrial cy39200v484-83bbi bb484 484-lead fine pitch ball grid array delta39k part numbers (ordering information) (continued) device speed (mhz) ordering code package name package type self-boot solution operating range cpld boot eeprom [17] part numbers (ordering information) device speed (mhz) ordering code package name package type operating range 2 mbit 15 at17lv002-10jc 20j 20-lead plastic leaded chip carrier commercial 10 at17lv002-10jc 20j 20-lead plastic leaded chip carrier industrial 1 mbit 15 at17lv010-10jc 20j 20-lead plastic leaded chip carrier commercial 10 at17lv010-10ji 20j 20-lead plastic leaded chip carrier industrial 512 kbit 15 at17lv512-10jc 20j 20-lead plastic leaded chip carrier commercial 10 at17lv512-10ji 20j 20-lead plastic leaded chip carrier industrial recommended atmel cpld boot eeprom for corresponding delta39k cplds cpld device recommended boot eeprom 39k30 at17lv512 39k50 at17lv512 39k100 at17lv010 39k165 at17lv002 39k200 at17lv002
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 41 of 86 package diagrams 51-85069-*b 208-lead enhanced quad flat pack (eqfp) nt208
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 42 of 86 package diagrams (continued) 388-lead ball grid array mg388 51-85103-*c
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 43 of 86 package diagrams (continued) bottom view top view 10987654321 a b c d e f g h j k pin 1 corner pin 1 corner 0.20(4x) ?0.25mcab ?0.05mc ?0.450.05(256x)-cpld devices (37k & 39k) 0.25 c 0.700.05 c seating plane 0.15 c 16 15 14 13 12 11 t r p m n l n t r p m l k j f g h e d a c b 16 15 13 14 12 10 11 9 28 7 6 5 4 3 1 a b ?0.500.05(256x)-all other devices a1 0.36 0.56 a 1.40 max. 1.60 max. reference jedec mo-192 15.00 1.00 0.35 a 17.000.10 7.50 7.50 15.00 17.000.10 1.00 a1 -0.05 +0.10 256-ball fbga (17 x 17 mm) bb256 51-85108-*d
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 44 of 86 package diagrams (continued) a 22 0.10(4x) ?0.600.10(484x) ?0.25mcab ?0.05 m c a1 corner b c d e f g h j k l m n p r t u v w y aa ab 21 20 19 18 17 16 15 14 13 12 11 10987654321 21.00 y u v t r m p n l k g j h f e b d c a aa ab w 22 15 19 20 21 17 18 16 12 14 13 10 11 9 578 6 4 23 1 1.00 21.00 1.00 a1 corner 0.25 c seating plane c 0.20 c top view bottom view 23.000.10 23.000.10 0.56 0.500.10 1.90 max a b 10.50 10.50 0.700.05 484-ball fbga (23 mm x 23 mm x 1.6 mm) bb484 51-85124-*d
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 45 of 86 pin tables package diagrams (continued) 676-ball fbga (27 x 27 x 1.6 mm) bb676/mb676 51-85125-*b table 8. pin definition table pin name function description gclk0-3 input global clock signals 0 through 3 gctl0-3 input global control signals 0 through 3 gnd ground ground io/v ref0 input/output dual function pin: io or reference voltage for bank 0 io/v ref1 input/output dual function pin: io or reference voltage for bank 1 io/v ref2 input/output dual function pin: io or reference voltage for bank 2 io/v ref3 input/output dual function pin: io or reference voltage for bank 3 io/v ref4 input/output dual function pin: io or reference voltage for bank 4 io/v ref5 input/output dual function pin: io or reference voltage for bank 5 io/v ref6 input/output dual function pin: io or reference voltage for bank 6 io/v ref7 input/output dual function pin: io or reference voltage for bank 7 io input/output input or output pin io6/lock input/output dual function pin: io in bank 6 or pll lock output signal msel input mode select pin (see table 9 )
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 46 of 86 reconfig input pin to start configuration of delta39k tclk input jtag test clock tdi input jtag test data in tdo output jtag test data out tms input jtag test mode select v cc power operating voltage v ccio0 power v cc for i/o bank 0 v ccio1 power v cc for i/o bank 1 v ccio2 power v cc for i/o bank 2 v ccio3 power v cc for i/o bank 3 v ccio4 power v cc for i/o bank 4 v ccio5 power v cc for i/o bank 5 v ccio6 power v cc for i/o bank 6 v ccio7 power v cc for i/o bank 7 v ccjtag power v cc for jtag pins v cccnfg power v cc for configuration port v ccpll [18] power v cc for pll v ccprg power v cc for programming the self-boot? solution embedded boot prom config_done output flag indicating that configuration is complete cclk output configuration clock for serial interface with the external boot prom cce output chip select for the external boot prom (active low) data input pin to receive configuration data from the external boot prom reset output reset signal to interface with the external boot prom table 8. pin definition table pin name function description table 9. mode select (msel) pin connectivity table gnd delta39k - self-boot? solution v cccnfg delta39k - with external boot prom table 10. i/o banks for global clock and global control pins (in all densities and packages) gclk[0] gctl[0] gclk[1] gctl[1] gclk[2] gctl[2] gclk[3] gctl[3] bank number 0567 table 11. 208 eqfp/pqfp pin table pin cy39030 cy39050 cy39100 cy39165 cy39200 1 gctl0 gctl0 gctl0 gctl0 gctl0 2 gnd gnd gnd gnd gnd 3 gclk0 gclk0 gclk0 gclk0 gclk0 4 gnd gnd gnd gnd gnd 5 io0 io0 io0 io0 io0 6 io0 io0 io0 io0 io0 7 io0 io0 io0 io0 io0 8io/v ref0 io/v ref0 io/v ref0 io/v ref0 io/v ref0 9 io0 io0 io0 io0 io0 10 io0 io0 io0 io0 io0 11 v ccio0 v ccio0 v ccio0 v ccio0 v ccio0 note: 18. the pll is available in delta39k ?v? devices (2.5v/3.3v) and not in delta39k ?z? devices (1.8v). in delta39k ?z? devices, co nnect v ccpll to v cc .
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 47 of 86 12 io0 io0 io0 io0 io0 13 io0 io0 io0 io0 io0 14 io0 io0 io0 io0 io0 15 io0 io0 io0 io0 io0 16 io/v ref0 io/v ref0 io/v ref0 io/v ref0 io/v ref0 17 io0 io0 io0 io0 io0 18 io0 io0 io0 io0 io0 19 io0 io0 io0 io0 io0 20 v ccio0 v ccio0 v ccio0 v ccio0 v ccio0 21 [19] io0 io0 io0 io0 io0 22 [19] io0 io0 io0 io0 io0 23 v cc v cc v cc v cc v cc 24 gnd gnd gnd gnd gnd 25 nc nc v cc v cc v cc 26 nc nc gnd gnd gnd 27 [19] io/v ref0 io/v ref0 io/v ref0 io/v ref0 io/v ref0 28 v ccio0 v ccio0 v ccio0 v ccio0 v ccio0 29 v ccio1 v ccio1 v ccio1 v ccio1 v ccio1 30 [19] io/v ref1 io/v ref1 io/v ref1 io/v ref1 io/v ref1 31 [19] io1 io1 io1 io1 io1 32 [19] io1 io1 io1 io1 io1 33 io1 io1 io1 io1 io1 34 io1 io1 io1 io1 io1 35 v ccio1 v ccio1 v ccio1 v ccio1 v ccio1 36 gnd gnd gnd gnd gnd 37 io1 io1 io1 io1 io1 38 io1 io1 io1 io1 io1 39 io1 io1 io1 io1 io1 40 io/v ref1 io/v ref1 io/v ref1 io/v ref1 io/v ref1 41 io1 io1 io1 io1 io1 42 io1 io1 io1 io1 io1 43 io1 io1 io1 io1 io1 44 io1 io1 io1 io1 io1 45 v ccprg v ccprg v ccprg v ccprg v ccprg 46 v ccio1 v ccio1 v ccio1 v ccio1 v ccio1 47 gnd gnd gnd gnd gnd 48 io1 io1 io1 io1 io1 49 io/v ref1 io/v ref1 io/v ref1 io/v ref1 io/v ref1 50 io1 io1 io1 io1 io1 51 io1 io1 io1 io1 io1 52 v cccnfg v cccnfg v cccnfg v cccnfg v cccnfg 53 data data data data data 54 config_done config_done config_done config_done config_done 55 reset reset reset reset reset table 11. 208 eqfp/pqfp pin table (continued) pin cy39030 cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 48 of 86 56 reconfig reconfig reconfig reconfig reconfig 57 cce cce cce cce cce 58 cclk cclk cclk cclk cclk 59 v cccnfg v cccnfg v cccnfg v cccnfg v cccnfg 60 msel msel msel msel msel 61 io2 io2 io2 io2 io2 62 io2 io2 io2 io2 io2 63 io2 io2 io2 io2 io2 64 io/v ref2 io/v ref2 io/v ref2 io/v ref2 io/v ref2 65 io2 io2 io2 io2 io2 66 v ccio2 v ccio2 v ccio2 v ccio2 v ccio2 67 gnd gnd gnd gnd gnd 68 io2 io2 io2 io2 io2 69 io2 io2 io2 io2 io2 70 io2 io2 io2 io2 io2 71 io2 io2 io2 io2 io2 72 io/v ref2 io/v ref2 io/v ref2 io/ vref2 io/v ref2 73 gnd gnd gnd gnd gnd 74 v ccio2 v ccio2 v ccio2 v ccio2 v ccio2 75 v cc v cc v cc v cc v cc 76 gnd gnd gnd gnd gnd 77 nc nc v cc v cc v cc 78 nc nc gnd gnd gnd 79 io2 io2 io2 io2 io2 80 io/v ref2 io/v ref2 io/v ref2 io/v ref2 io/v ref2 81 [19] io2 io2 io2 io2 io2 82 [19] io2 io2 io2 io2 io2 83 [19] io2 io2 io2 io2 io2 84 v ccio2 v ccio2 v ccio2 v ccio2 v ccio2 85 v ccio3 v ccio3 v ccio3 v ccio3 v ccio3 86 [19] io3 io3 io3 io3 io3 87 [19] io3 io3 io3 io3 io3 88 [19] io/v ref3 io/v ref3 io/v ref3 io/v ref3 io/v ref3 89 v ccio3 v ccio3 v ccio3 v ccio3 v ccio3 90 gnd gnd gnd gnd gnd 91 io3 io3 io3 io3 io3 92 io3 io3 io3 io3 io3 93 io3 io3 io3 io3 io3 94 io3 io3 io3 io3 io3 95 io3 io3 io3 io3 io3 96 io/v ref3 io/v ref3 io/v ref3 io/v ref3 io/v ref3 97 io3 io3 io3 io3 io3 98 v ccio3 v ccio3 v ccio3 v ccio3 v ccio3 99 io3 io3 io3 io3 io3 table 11. 208 eqfp/pqfp pin table (continued) pin cy39030 cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 49 of 86 100 gnd gnd gnd gnd gnd 101 io3 io3 io3 io3 io3 102 io3 io3 io3 io3 io3 103 io3 io3 io3 io3 io3 104 io/v ref3 io/v ref3 io/v ref3 io/v ref3 io/v ref3 105 io4 io4 io4 io4 io4 106 io4 io4 io4 io4 io4 107 io4 io4 io4 io4 io4 108 io/v ref4 io/v ref4 io/v ref4 io/v ref4 io/v ref4 109 io4 io4 io4 io4 io4 110 io4 io4 io4 io4 io4 111 v ccio4 v ccio4 v ccio4 v ccio4 v ccio4 112 gnd gnd gnd gnd gnd 113 io4 io4 io4 io4 io4 114 v ccprg v ccprg v ccprg v ccprg v ccprg 115 io4 io4 io4 io4 io4 116 io/v ref4 io/v ref4 io/v ref4 io/v ref4 io/v ref4 117 io4 io4 io4 io4 io4 118 io4 io4 io4 io4 io4 119 io4 io4 io4 io4 io4 120 io4 io4 io4 io4 io4 121 io4 io4 io4 io4 io4 122 [19] io/v ref4 io/v ref4 io/v ref4 io/v ref4 io/v ref4 123 [19] io4 io4 io4 io4 io4 124 v ccio4 v ccio4 v ccio4 v ccio4 v ccio4 125 gnd gnd gnd gnd gnd 126 [19] io4 io4 io4 io4 io4 127 v cc v cc v cc v cc v cc 128 gnd gnd gnd gnd gnd 129 nc nc v cc v cc v cc 130 nc nc gnd gnd gnd 131 v ccio4 v ccio4 v ccio4 v ccio4 v ccio4 132 v ccio5 v ccio5 v ccio5 v ccio5 v ccio5 133 [19] io5 io5 io5 io5 io5 134 [19] io5 io5 io5 io5 io5 135 [19] io/v ref5 io/v ref5 io/v ref5 io/v ref5 io/v ref5 136 io5 io5 io5 io5 io5 137 io5 io5 io5 io5 io5 138 v ccio5 v ccio5 v ccio5 v ccio5 v ccio5 139 io5 io5 io5 io5 io5 140 io5 io5 io5 io5 io5 141 io5 io5 io5 io5 io5 142 io/v ref5 io/v ref5 io/v ref5 io/v ref5 io/v ref5 143 io5 io5 io5 io5 io5 table 11. 208 eqfp/pqfp pin table (continued) pin cy39030 cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 50 of 86 144 io5 io5 io5 io5 io5 145 io5 io5 io5 io5 io5 146 io5 io5 io5 io5 io5 147 io5 io5 io5 io5 io5 148 v ccio5 v ccio5 v ccio5 v ccio5 v ccio5 149 io/v ref5 io/v ref5 io/v ref5 io/v ref5 io/v ref5 150 io5 io5 io5 io5 io5 151 io5 io5 io5 io5 io5 152 gnd gnd gnd gnd gnd 153 gclk1 gclk1 gclk1 gclk1 gclk1 154 gnd gnd gnd gnd gnd 155 gctl1 gctl1 gctl1 gctl1 gctl1 156 tdo tdo tdo tdo tdo 157 tclk tclk tclk tclk tclk 158 tdi tdi tdi tdi tdi 159 v ccjtag v ccjtag v ccjtag v ccjtag v ccjtag 160 gclk2 gclk2 gclk2 gclk2 gclk2 161 gnd gnd gnd gnd gnd 162 tms tms tms tms tms 163 gctl2 gctl2 gctl2 gctl2 gctl2 164 io6 io6 io6 io6 io6 165 io6 io6 io6 io6 io6 166 io6 io6 io6 io6 io6 167 io/v ref6 io/v ref6 io/v ref6 io/v ref6 io/v ref6 168 io6 io6 io6 io6 io6 169 v ccio6 v ccio6 v ccio6 v ccio6 v ccio6 170 io6 io6 io6 io6 io6 171 io6 io6 io6 io6 io6 172 io6 io6 io6 io6 io6 173 io/v ref6 io/v ref6 io/v ref6 io/v ref6 io/v ref6 174 io6 io6 io6 io6 io6 175 io6 io6 io6 io6 io6 176 io6 io6 io6 io6 io6 177 gnd gnd gnd gnd gnd 178 v ccio6 v ccio6 v ccio6 v ccio6 v ccio6 179 v ccpll v ccpll v ccpll v ccpll v ccpll 180 gnd gnd gnd gnd gnd 181 v cc v cc v cc v cc v cc 182 gnd gnd gnd gnd gnd 183 [19] io/v ref6 io/v ref6 io/v ref6 io/v ref6 io/v ref6 184 [19] io6 io6 io6 io6 io6 185 [19] io6/lock io6/lock io6/lock io6/lock io6/lock 186 v ccio6 v ccio6 v ccio6 v ccio6 v ccio6 187 v ccio7 v ccio7 v ccio7 v ccio7 v ccio7 table 11. 208 eqfp/pqfp pin table (continued) pin cy39030 cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 51 of 86 188 [19] io7 io7 io7 io7 io7 189 [19] io7 io7 io7 io7 io7 190 [19] io/v ref7 io/v ref7 io/v ref7 io/v ref7 io/v ref7 191 v ccio7 v ccio7 v ccio7 v ccio7 v ccio7 192 io7 io7 io7 io7 io7 193 io7 io7 io7 io7 io7 194 io7 io7 io7 io7 io7 195 io7 io7 io7 io7 io7 196 io/v ref7 io/v ref7 io/v ref7 io/v ref7 io/v ref7 197 io7 io7 io7 io7 io7 198 io7 io7 io7 io7 io7 199 v ccio7 v ccio7 v ccio7 v ccio7 v ccio7 200 io7 io7 io7 io7 io7 201 io/v ref7 io/v ref7 io/v ref7 io/v ref7 io/v ref7 202 io7 io7 io7 io7 io7 203 io7 io7 io7 io7 io7 204 io7 io7 io7 io7 io7 205 gnd gnd gnd gnd gnd 206 gclk3 gclk3 gclk3 gclk3 gclk3 207 gnd gnd gnd gnd gnd 208 gctl3 gctl3 gctl3 gctl3 gctl3 table 11. 208 eqfp/pqfp pin table (continued) pin cy39030 cy39050 cy39100 cy39165 cy39200 table 12. 388 bga pin table pin cy39050 cy39100 cy39165 cy39200 a1 gnd gnd gnd gnd a2 nc io7 io7 io7 a3io7io7io7io7 a4io7io7io7io7 a5io7io7io7io7 a6io7io7io7io7 a7io7io7io7io7 a8 nc io/vref7 io/vref7 io/vref7 a9io7io7io7io7 a10 io7 io7 io7 io7 a11 io/v ref7 io/v ref7 io/v ref7 io/v ref7 a12 io7 io7 io7 io7 a13 [19] io7io7io7io7 a14 [19] io6io6io6io6 a15 io6 io6 io6 io6 a16 gnd gnd gnd gnd a17 io6 io6 io6 io6 a18 io6 io6 io6 io6 note: 19. capacitance on these i/o pins meets the pci spec (rev. 2.2), which requires idsel pin in a pci design to have capacitance le ss than or equal to 8 pf. in the document titled ?delta39k cpld family data sheet?, this spec is defined as c pci. all other i/o pins have a capacitance less than or equal to 10 pf.
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 52 of 86 a19 nc io6 io6 io6 a20 nc io6 io6 io6 a21 io6 io6 io6 io6 a22 io/v ref6 io/v ref6 io/v ref6 io/v ref6 a23 io6 io6 io6 io6 a24 io6 io6 io6 io6 a25 io6 io6 io6 io6 a26 gnd gnd gnd gnd b1io7io7io7io7 b2 nc io7 io7 io7 b3 nc io7 io7 io7 b4 nc io/v ref7 io/v ref7 io/v ref7 b5io7io7io7io7 b6 io/v ref7 io/v ref7 io/v ref7 io/v ref7 b7io7io7io7io7 b8io7io7io7io7 b9io7io7io7io7 b10 io/v ref7 io/v ref7 io/v ref7 io/v ref7 b11 io7 io7 io7 io7 b12 io7 io7 io7 io7 b13 [19] io7io7io7io7 b14 [19] io6io6io6io6 b15 io6 io6 io6 io6 b16 io6 io6 io6 io6 b17 io6/lock io6/lock io6/lock io6/lock b18 io6 io6 io6 io6 b19 io6 io6 io6 io6 b20 io/vref6 io/vref6 io/vref6 io/vref6 b21 io6 io6 io6 io6 b22 nc io6 io6 io6 b23 nc io6 io6 io6 b24 io6 io6 io6 io6 b25 io6 io6 io6 io6 b26 io6 io6 io6 io6 c1io0io0io0io0 c2 io/v ref7 io/v ref7 io/v ref7 io/v ref7 c3 nc io7 io7 io7 c4io7io7io7io7 c5io7io7io7io7 c6 nc io7 io7 io7 c7io7io7io7io7 c8io7io7io7io7 c9io7io7io7io7 c10 io7 io7 io7 io7 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 53 of 86 c11 io7 io7 io7 io7 c12 io7 io7 io7 io7 c13 [19] io7io7io7io7 c14 [19] io6io6io6io6 c15 io/v ref6 io/v ref6 io/v ref6 io/v ref6 c16 io6 io6 io6 io6 c17 nc io/v ref6 io/v ref6 io/v ref6 c18 io6 io6 io6 io6 c19 io6 io6 io6 io6 c20 io6 io6 io6 io6 c21 io6 io6 io6 io6 c22 nc io6 io6 io6 c23 nc io6 io6 io6 c24 io6 io6 io6 io6 c25 io/v ref6 io/v ref6 io/v ref6 io/v ref6 c26 io6 io6 io6 io6 d1io0io0io0io0 d2io0io0io0io0 d3 io/v ref0 io/v ref0 io/v ref0 io/v ref0 d4io7io7io7io7 d5 gctl3 gctl3 gctl3 gctl3 d6 nc io7 io7 io7 d7 gclk3 gclk3 gclk3 gclk3 d8 v ccio7 v ccio7 v ccio7 v ccio7 d9 v ccio7 v ccio7 v ccio7 v ccio7 d10 v ccio7 v ccio7 v ccio7 v ccio7 d11 io7 io7 io7 io7 d12 v ccio7 v ccio7 v ccio7 v ccio7 d13 v cc v cc v cc v cc d14 v ccio6 v ccio6 v ccio6 v ccio6 d15 v ccio6 v ccio6 v ccio6 v ccio6 d16 io6 io6 io6 io6 d17 v ccpll v ccpll v ccpll v ccpll d18 v ccio6 v ccio6 v ccio6 v ccio6 d19 v ccio6 v ccio6 v ccio6 v ccio6 d20 gclk2 gclk2 gclk2 gclk2 d21 nc io/v ref6 io/v ref6 io/v ref6 d22 gctl2 gctl2 gctl2 gctl2 d23 nc io6 io6 io6 d24 io5 io5 io5 io5 d25 tms tms tms tms d26 tclk tclk tclk tclk e1io0io0io0io0 e2io0io0io0io0 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 54 of 86 e3io0io0io0io0 e4 gctl0 gctl0 gctl0 gctl0 e23 gclk1 gclk1 gclk1 gclk1 e24 io5 io5 io5 io5 e25 tdi tdi tdi tdi e26 tdo tdo tdo tdo f1 nc io0 io0 io0 f2 nc io0 io0 io0 f3 nc io0 io0 io0 f4io0io0io0io0 f23 nc io5 io5 io5 f24 io5 io5 io5 io5 f25 io5 io5 io5 io5 f26 io5 io5 io5 io5 g1 io0 io0 io0 io0 g2 io0 io0 io0 io0 g3 io/v ref0 io/v ref0 io/v ref0 io/v ref0 g4 gclk0 gclk0 gclk0 gclk0 g23 gctl1 gctl1 gctl1 gctl1 g24 io/v ref5 io/v ref5 io/v ref5 io/v ref5 g25 io5 io5 io5 io5 g26 io5 io5 io5 io5 h1io0io0io0io0 h2 nc io0 io0 io0 h3 nc io0 io0 io0 h4 v ccio0 v ccio0 v ccio0 v ccio0 h23 v ccjtag v ccjtag v ccjtag v ccjtag h24 io5 io5 io5 io5 h25 io5 io5 io5 io5 h26 io5 io5 io5 io5 j1 nc io0 io0 io0 j2 nc io/v ref0 io/v ref0 io/v ref0 j3 nc io0 io0 io0 j4 v ccio0 v ccio0 v ccio0 v ccio0 j23 v ccio5 v ccio5 v ccio5 v ccio5 j24 nc io/v ref5 io/v ref5 io/v ref5 j25 io5 io5 io5 io5 j26 io5 io5 io5 io5 k1 nc io0 io0 io0 k2 nc io0 io0 io0 k3 nc io0 io0 io0 k4 v cc v cc v cc v cc k23 v ccio5 v ccio5 v ccio5 v ccio5 k24 io5 io5 io5 io5 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 55 of 86 k25 nc io5 io5 io5 k26 nc io5 io5 io5 l1io0io0io0io0 l2io0io0io0io0 l3io0io0io0io0 l4io0io0io0io0 l11 gnd gnd gnd gnd l12 gnd gnd gnd gnd l13 gnd gnd gnd gnd l14 gnd gnd gnd gnd l15 gnd gnd gnd gnd l16 gnd gnd gnd gnd l23 nc io5 io5 io5 l24 io/v ref5 io/v ref5 io/v ref5 io/v ref5 l25 nc io5 io5 io5 l26 nc io5 io5 io5 m1io0io0io0io0 m2 [19] io0io0io0io0 m3 [19] io0io0io0io0 m4 v ccio0 v ccio0 v ccio0 v ccio0 m11 gnd gnd gnd gnd m12 gnd gnd gnd gnd m13 gnd gnd gnd gnd m14 gnd gnd gnd gnd m15 gnd gnd gnd gnd m16 gnd gnd gnd gnd m23 v ccio5 v ccio5 v ccio5 v ccio5 m24 nc io5 io5 io5 m25 nc io5 io5 io5 m26 nc io5 io5 io5 n1 nc vcc vcc vcc n2 io/v ref0 io/v ref0 io/v ref0 io/v ref0 n3 [19] io0io0io0io0 n4 [19] io1io1io1io1 n11 gnd gnd gnd gnd n12 gnd gnd gnd gnd n13 gnd gnd gnd gnd n14 gnd gnd gnd gnd n15 gnd gnd gnd gnd n16 gnd gnd gnd gnd n23 [19] io5io5io5io5 n24 io5 io5 io5 io5 n25 io5 io5 io5 io5 n26 io/v ref5 io/v ref5 io/v ref5 io/v ref5 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 56 of 86 p1io1io1io1io1 p2 io/v ref1 io/v ref1 io/v ref1 io/v ref1 p3 [19] io1io1io1io1 p4 [19] io1io1io1io1 p11 gnd gnd gnd gnd p12 gnd gnd gnd gnd p13 gnd gnd gnd gnd p14 gnd gnd gnd gnd p15 gnd gnd gnd gnd p16 gnd gnd gnd gnd p23 v cc v cc v cc v cc p24 [19] io5io5io5io5 p25 [19] io5io5io5io5 p26 nc v cc v cc v cc r1io1io1io1io1 r2io1io1io1io1 r3 nc io1 io1 io1 r4 v ccio1 v ccio1 v ccio1 v ccio1 r11 gnd gnd gnd gnd r12 gnd gnd gnd gnd r13 gnd gnd gnd gnd r14 gnd gnd gnd gnd r15 gnd gnd gnd gnd r16 gnd gnd gnd gnd r23 v ccio4 v ccio4 v ccio4 v ccio4 r24 [19] io4io4io4io4 r25 [19] io4io4io4io4 r26 nc io5 io5 io5 t1 nc io1 io1 io1 t2 nc io1 io1 io1 t3 nc io/v ref1 io/v ref1 io/v ref1 t4 nc io1 io1 io1 t11 gnd gnd gnd gnd t12 gnd gnd gnd gnd t13 gnd gnd gnd gnd t14 gnd gnd gnd gnd t15 gnd gnd gnd gnd t16 gnd gnd gnd gnd t23 [19] io4io4io4io4 t24 io4 io4 io4 io4 t25 io/v ref4 io/v ref4 io/v ref4 io/v ref4 t26 io4 io4 io4 io4 u1 nc io1 io1 io1 u2 nc io1 io1 io1 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 57 of 86 u3 nc io1 io1 io1 u4 v ccprg v ccprg v ccprg v ccprg u23 v ccprg v ccprg v ccprg v ccprg u24 io4 io4 io4 io4 u25 io4 io4 io4 io4 u26 nc io4 io4 io4 v1 nc io1 io1 io1 v2 nc io1 io1 io1 v3io1io1io1io1 v4 v ccio1 v ccio1 v ccio1 v ccio1 v23 v ccio4 v ccio4 v ccio4 v ccio4 v24 nc io4 io4 io4 v25 nc io4 io4 io4 v26 nc io4 io4 io4 w1io1io1io1io1 w2io1io1io1io1 w3 io/v ref1 io/v ref1 io/v ref1 io/v ref1 w4 v ccio1 v ccio1 v ccio1 v ccio1 w23 v ccio4 v ccio4 v ccio4 v ccio4 w24 nc io4 io4 io4 w25 nc io/v ref4 io/v ref4 io/v ref4 w26 nc io4 io4 io4 y1io1io1io1io1 y2io1io1io1io1 y3io1io1io1io1 y4io1io1io1io1 y23 nc io4 io4 io4 y24 nc io4 io4 io4 y25 nc io4 io4 io4 y26 io4 io4 io4 io4 aa1io1io1io1io1 aa2io1io1io1io1 aa3 io/v ref1 io/v ref1 io/v ref1 io/v ref1 aa4io1io1io1io1 aa23io4io4io4io4 aa24io4io4io4io4 aa25 io/v ref4 io/v ref4 io/v ref4 io/v ref4 aa26io4io4io4io4 ab1 v cccnfg v cccnfg v cccnfg v cccnfg ab2 config_done config_done config_done config_done ab3io1io1io1io1 ab4io1io1io1io1 ab23io4io4io4io4 ab24io4io4io4io4 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 58 of 86 ab25io4io4io4io4 ab26io4io4io4io4 ac1datadatadatadata ac2 reconfig reconfig reconfig reconfig ac3 io2 io2 io2 io2 ac4 io2 io2 io2 io2 ac5 io2 io2 io2 io2 ac6 io2 io2 io2 io2 ac7 nc io2 io2 io2 ac8 v ccio2 v ccio2 v ccio2 v ccio2 ac9 v ccio2 v ccio2 v ccio2 v ccio2 ac10 v cccnfg v cccnfg v cccnfg v cccnfg ac11io2io2io2io2 ac12 v ccio2 v ccio2 v ccio2 v ccio2 ac13 v ccio2 v ccio2 v ccio2 v ccio2 ac14 v ccio3 v ccio3 v ccio3 v ccio3 ac15 v ccio3 v ccio3 v ccio3 v ccio3 ac16io3io3io3io3 ac17 nc v cc v cc v cc ac18 v ccio3 v ccio3 v ccio3 v ccio3 ac19 v ccio3 v ccio3 v ccio3 v ccio3 ac20io3io3io3io3 ac21io3io3io3io3 ac22io3io3io3io3 ac23 io/v ref4 io/v ref4 io/v ref4 io/v ref4 ac24io4io4io4io4 ac25io4io4io4io4 ac26io4io4io4io4 ad1 reset reset reset reset ad2 cclk cclk cclk cclk ad3 io/v ref2 io/v ref2 io/v ref2 io/v ref2 ad4 io2 io2 io2 io2 ad5 io/v ref2 io/v ref2 io/v ref2 io/v ref2 ad6 io2 io2 io2 io2 ad7 nc io2 io2 io2 ad8 nc io/v ref2 io/v ref2 io/v ref2 ad9 io2 io2 io2 io2 ad10 io/v ref2 io/v ref2 io/v ref2 io/v ref2 ad11io2io2io2io2 ad12io2io2io2io2 ad13 io/v ref2 io/v ref2 io/v ref2 io/v ref2 ad14 [19] io2io2io2io2 ad15 [19] io3io3io3io3 ad16io3io3io3io3 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 59 of 86 ad17io3io3io3io3 ad18 io/v ref3 io/v ref3 io/v ref3 io/v ref3 ad19io3io3io3io3 ad20io3io3io3io3 ad21io3io3io3io3 ad22io3io3io3io3 ad23io3io3io3io3 ad24 nc io3 io3 io3 ad25 io/v ref3 io/v ref3 io/v ref3 io/v ref3 ad26io3io3io3io3 ae1 cce cce cce cce ae2 msel msel msel msel ae3io2io2io2io2 ae4io2io2io2io2 ae5io2io2io2io2 ae6 nc io2 io2 io2 ae7 nc io/v ref2 io/v ref2 io/v ref2 ae8io2io2io2io2 ae9io2io2io2io2 ae10io2io2io2io2 ae11 io2 io2 io2 io2 ae12io2io2io2io2 ae13 [19] io2io2io2io2 ae14 [19] io2io2io2io2 ae15 io/v ref3 io/v ref3 io/v ref3 io/v ref3 ae16io3io3io3io3 ae17io3io3io3io3 ae18io3io3io3io3 ae19io3io3io3io3 ae20 io/v ref3 io/v ref3 io/v ref3 io/v ref3 ae21 nc io3 io3 io3 ae22io3io3io3io3 ae23 nc io/v ref3 io/v ref3 io/v ref3 ae24 nc io3 io3 io3 ae25io3io3io3io3 ae26io3io3io3io3 af1 gnd gnd gnd gnd af2 io2 io2 io2 io2 af3 io2 io2 io2 io2 af4 io2 io2 io2 io2 af5 io2 io2 io2 io2 af6 nc io2 io2 io2 af7 nc io2 io2 io2 af8 nc io2 io2 io2 table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 60 of 86 af9 nc io2 io2 io2 af10io2io2io2io2 af11 gnd gnd gnd gnd af12io2io2io2io2 af13 v cc v cc v cc v cc af14 [19] io3io3io3io3 af15 [19] io3io3io3io3 af16io3io3io3io3 af17io3io3io3io3 af18io3io3io3io3 af19io3io3io3io3 af20io3io3io3io3 af21 nc io3 io3 io3 af22 nc io/v ref3 io/v ref3 io/v ref3 af23io3io3io3io3 af24 nc io3 io3 io3 af25 nc io3 io3 io3 af26 gnd gnd gnd gnd table 12. 388 bga pin table (continued) pin cy39050 cy39100 cy39165 cy39200 table 13. 256 fbga pin table pin cy39030 cy39050 cy39100 a1 gnd gnd gnd a2 io7 io7 io7 a3 io7 io7 io7 a4 io7 io7 io7 a5 io7 io7 io7 a6 io/v ref7 io/v ref7 io/v ref7 a7 nc io/v ref7 io/v ref7 a8 io6/lock io6/lock io6/lock a9 io6 io6 io6 a10 io/v ref6 io/v ref6 io/v ref6 a11 io/v ref6 io/v ref6 io/v ref6 a12 io6 io6 io6 a13 io6 io6 io6 a14 io6 io6 io6 a15 io6 io6 io6 a16 gnd gnd gnd b1 io0 io0 io0 b2 gnd gnd gnd b3 io7 io7 io7 b4 io7 io7 io7 b5 io7 io7 io7 b6 v ccio7 v ccio7 v ccio7 b7 v cc v cc v cc
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 61 of 86 b8 io/v ref7 io/v ref7 io/v ref7 b9 nc io/vr ef6 io/v ref6 b10 v ccpll v ccpll v ccpll b11 v ccio6 v ccio6 v ccio6 b12 io6 io6 io6 b13 io6 io6 io6 b14 io6 io6 io6 b15 gnd gnd gnd b16 tdo tdo tdo c1 io0 io0 io0 c2 io0 io0 io0 c3 gnd gnd gnd c4 io7 io7 io7 c5 io7 io7 io7 c6 v ccio7 v ccio7 v ccio7 c7 v ccio7 v ccio7 v ccio7 c8 [19] nc io7 io7 c9 [19] io6 io6 io6 c10 v ccio6 v ccio6 v ccio6 c11 v ccio6 v ccio6 v ccio6 c12 io6 io6 io6 c13 io6 io6 io6 c14 gnd gnd gnd c15 tdi tdi tdi c16 io5 io5 io5 d1 io0 io0 io0 d2 io0 io0 io0 d3 io0 io0 io0 d4 gnd gnd gnd d5 io7 io7 io7 d6 io/v ref7 io/v ref7 io/v ref7 d7 io7 io7 io7 d8 [19] io7 io7 io7 d9 [19] nc io6 io6 d10 io6 io6 io6 d11 io/v ref6 io/v ref6 io/v ref6 d12 io6 io6 io6 d13 gnd gnd gnd d14 tclk tclk tclk d15 io5 io5 io5 d16 io5 io5 io5 e1 io0 io0 io0 e2 io0 io0 io0 e3 io0 io0 io0 table 13. 256 fbga pin table (continued) pin cy39030 cy39050 cy39100
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 62 of 86 e4 io0 io0 io0 e5 io7 io7 io7 e6 io7 io7 io7 e7 io7 io7 io7 e8 [19] io7 io7 io7 e9 [19] io6 io6 io6 e10 io6 io6 io6 e11 io6 io6 io6 e12 tms tms tms e13 io5 io5 io5 e14 io5 io5 io5 e15 io5 io5 io5 e16 io5 io5 io5 f1 io0 io0 io0 f2 v cc v cc v cc f3 v ccio0 v ccio0 v ccio0 f4 io/v ref0 io/v ref0 io/v ref0 f5 io0 io0 io0 f6 io7 io7 io7 f7 gctl3 gctl3 gctl3 f8 gclk3 gclk3 gclk3 f9 gctl2 gctl2 gctl2 f10 gclk2 gclk2 gclk2 f11 io5 io5 io5 f12 io5 io5 io5 f13 io/v ref5 io/v ref5 io/v ref5 f14 v ccio5 v ccio5 v ccio5 f15 v ccjtag v ccjtag v ccjtag f16 io5 io5 io5 g1 io0 io0 io0 g2 nc nc v cc g3 v ccio0 v ccio0 v ccio0 g4 io/v ref0 io/v ref0 io/v ref0 g5 io0 io0 io0 g6 gctl0 gctl0 gctl0 g7 gnd gnd gnd g8 gnd gnd gnd g9 gnd gnd gnd g10 gnd gnd gnd g11 gctl1 gctl1 gctl1 g12 io5 io5 io5 g13 io/v ref5 io/v ref5 io/v ref5 g14 v ccio5 v ccio5 v ccio5 g15 nc nc vcc table 13. 256 fbga pin table (continued) pin cy39030 cy39050 cy39100
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 63 of 86 g16 io5 io5 io5 h1 [19] io0 io0 io0 h2 [19] io0 io0 io0 h3 [19] io0 io0 io0 h4 io/v ref0 io/v ref0 io/v ref0 h5 io0 io0 io0 h6 gclk0 gclk0 gclk0 h7 gnd gnd gnd h8 gnd gnd gnd h9 gnd gnd gnd h10 gnd gnd gnd h11 gclk1 gclk1 gclk1 h12 io5 io5 io5 h13 io/v ref5 io/v ref5 io/v ref5 h14 [19] io5 io5 io5 h15 [19] io5 io5 io5 h16 [19] io5 io5 io5 j1 io1 io1 io1 j2 io1 io1 io1 j3 [19] io1 io1 io1 j4 [19] io1 io1 io1 j5 [19] io1 io1 io1 j6 io1 io1 io1 j7 gnd gnd gnd j8 gnd gnd gnd j9 gnd gnd gnd j10 gnd gnd gnd j11 io4 io4 io4 j12 [19] io4 io4 io4 j13 [19] io4 io4 io4 j14 [19] io4 io4 io4 j15 io5 io5 io5 j16 io5 io5 io5 k1 io1 io1 io1 k2 v ccprg v ccprg v ccprg k3 v ccio1 v ccio1 v ccio1 k4 io/v ref1 io/v ref1 io/v ref1 k5 io1 io1 io1 k6 io1 io1 io1 k7 gnd gnd gnd k8 gnd gnd gnd k9 gnd gnd gnd k10 gnd gnd gnd k11 io4 io4 io4 table 13. 256 fbga pin table (continued) pin cy39030 cy39050 cy39100
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 64 of 86 k12 io4 io4 io4 k13 io/v ref4 io/v ref4 io/v ref4 k14 v ccio4 v ccio4 v ccio4 k15 v ccprg v ccprg v ccprg k16 io4 io4 io4 l1 io1 io1 io1 l2 nc nc v cc l3 v ccio1 v ccio1 v ccio1 l4 io/v ref1 io/v ref1 io/v ref1 l5 v cccnfg v cccnfg v cccnfg l6 config_done config_done config_done l7 io2 io2 io2 l8 [19] io2 io2 io2 l9 [19] io3 io3 io3 l10 io3 io3 io3 l11 io3 io3 io3 l12 io4 io4 io4 l13 io/v ref4 io/v ref4 io/v ref4 l14 v ccio4 v ccio4 v ccio4 l15 v cc v cc v cc l16 io4 io4 io4 m1 io1 io1 io1 m2 io1 io1 io1 m3 io1 io1 io1 m4 data data data m5 reconfig reconfig reconfig m6 io2 io2 io2 m7 io2 io2 io2 m8 [19] io2 io2 io2 m9 [19] io3 io3 io3 m10 io3 io3 io3 m11 io3 io3 io3 m12 io3 io3 io3 m13 io4 io4 io4 m14 io4 io4 io4 m15 io4 io4 io4 m16 io4 io4 io4 n1 io/v ref1 io/v ref1 io/v ref1 n2 io1 io1 io1 n3 io1 io1 io1 n4 gnd gnd gnd n5 msel msel msel n6 io/v ref2 io/v ref2 io/v ref2 n7 io/v ref2 io/v ref2 io/v ref2 table 13. 256 fbga pin table (continued) pin cy39030 cy39050 cy39100
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 65 of 86 n8 [19] io2 io2 io2 n9 [19] io3 io3 io3 n10 io/v ref3 io/v ref3 io/v ref3 n11 io/v ref3 io/v ref3 io/v ref3 n12 io3 io3 io3 n13 gnd gnd gnd n14 io4 io4 io4 n15 io4 io4 io4 n16 io/v ref4 io/v ref4 io/v ref4 p1 io1 io1 io1 p2 io1 io1 io1 p3 gnd gnd gnd p4 cce cce cce p5 io2 io2 io2 p6 v ccio2 v ccio2 v ccio2 p7 v ccio2 v ccio2 v ccio2 p8 io2 io2 io2 p9 io2 io2 io2 p10 v ccio3 v ccio3 v ccio3 p11 v ccio3 v ccio3 v ccio3 p12 io3 io3 io3 p13 io3 io3 io3 p14 gnd gnd gnd p15 io4 io4 io4 p16 io4 io4 io4 r1 io1 io1 io1 r2 gnd gnd gnd r3 cclk cclk cclk r4 io2 io2 io2 r5 io2 io2 io2 r6 v cccnfg v cccnfg v cccnfg r7 v ccio2 v ccio2 v ccio2 r8 io2 io2 io2 r9 io2 io2 io2 r10 v cc v cc v cc r11 v ccio3 v ccio3 v ccio3 r12 io3 io3 io3 r13 io3 io3 io3 r14 io3 io3 io3 r15 gnd gnd gnd r16 io4 io4 io4 t1 gnd gnd gnd t2 reset reset reset t3 io2 io2 io2 table 13. 256 fbga pin table (continued) pin cy39030 cy39050 cy39100
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 66 of 86 t4 io2 io2 io2 t5 io2 io2 io2 t6 io/v ref2 io/v ref2 io/v ref2 t7 nc io/v ref2 io/v ref2 t8 io2 io2 io2 t9 io2 io2 io2 t10 nc io/v ref3 io/v ref3 t11 io/v ref3 io/v ref3 io/v ref3 t12 io3 io3 io3 t13 io3 io3 io3 t14 io3 io3 io3 t15 io3 io3 io3 t16 gnd gnd gnd table 13. 256 fbga pin table (continued) pin cy39030 cy39050 cy39100 table 14. 484 fbga pin table pin cy39050 cy39100 cy39165 cy39200 a1 gnd gnd gnd gnd a2 gnd gnd gnd gnd a3 nc nc io/v ref7 io/v ref7 a4 nc nc io/v ref7 io/v ref7 a5 io7 io7 io7 io7 a6 io7 io7 io7 io7 a7 nc io7 io7 io7 a8 io7 io7 io7 io7 a9 io7 io7 io7 io7 a10 io7 io7 io7 io7 a11 gnd gnd gnd gnd a12 gnd gnd gnd gnd a13 io6 io6 io6 io6 a14 io6 io6 io6 io6 a15 io6 io6 io6 io6 a16 nc io6 io6 io6 a17 io6 io6 io6 io6 a18 io6 io6 io6 io6 a19 nc nc nc io/v ref6 a20 nc nc nc io6 a21 gnd gnd gnd gnd a22 gnd gnd gnd gnd b1 gnd gnd gnd gnd b2 gnd gnd gnd gnd b3 nc nc io7 io7 b4 v ccio7 v ccio7 v ccio7 v ccio7 b5 nc io7 io7 io7 b6 io7 io7 io7 io7
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 67 of 86 b7 nc io7 io7 io7 b8 io/v ref7 io/v ref7 io/v ref7 io/v ref7 b9 nc nc v ccio7 v ccio7 b10 io7 io7 io7 io7 b11 io7 io7 io7 io7 b12 io6 io6 io6 io6 b13 io6 io6 io6 io6 b14 nc nc v ccio6 v ccio6 b15 io/v ref6 io/v ref6 io/v ref6 io/v ref6 b16 nc io6 io6 [20] io6 b17 io6 io6 io6 io6 b18 io6 io6 io6 io6 b19 v ccio6 v ccio6 v ccio6 v ccio6 b20 nc nc nc io6 b21 gnd gnd gnd gnd b22 gnd gnd gnd gnd c1 nc nc io7 io7 c2 nc nc io7 io7 c3 nc nc io7 io7 c4 nc io7 io7 io7 c5 nc io7 io7 io7 c6 io7 io7 io7 io7 c7 nc io7 io7 io7 c8 io7 io7 io7 io7 c9 io7 io7 io7 io7 c10 io/ vref7 io/ vref7 io/v ref7 io/v ref7 c11 io7 io7 io7 io7 c12 io6 io6 io6 io6 c13 nc io/v ref6 io/v ref6 io/v ref6 c14 io6 io6 io6 io6 c15 io6 io6 io6 [20] io6 c16 nc io6 io6 io6 c17 io6 io6 io6 io6 c18 io6 io6 io6 io6 c19 io6 io6 io6 io6 c20 nc nc nc io6 c21 nc nc nc io6 c22 nc nc nc io6 d1 nc nc io/v ref0 io/v ref0 d2 v ccio0 v ccio0 v ccio0 v ccio0 d3 nc nc io0 io0 d4 gnd gnd gnd gnd d5 nc io7 io7 io7 d6 nc io7 io7 io7 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 68 of 86 d7 io7 io7 io7 io7 d8 io7 io7 io7 io7 d9 io/v ref7 io/v ref7 io/v ref7 io/v ref7 d10 nc io/v ref7 io/v ref7 io/v ref7 d11 io6/lock io6/lock io6/lock io6/lock d12 io6 io6 io6 io6 d13 io/v ref6 io/v ref6 io/v ref6 io/v ref6 d14 io/v ref6 io/v ref6 io/v ref6 io/v ref6 d15 io6 io6 io6 io6 d16 nc io6 io6 io6 d17 nc io6 io6 io6 d18 io6 io6 io6 io6 d19 gnd gnd gnd gnd d20 nc nc io5 io5 d21 v ccio5 v ccio5 v ccio5 v ccio5 d22 nc nc io/v ref5 io/v ref5 e1 nc nc io0 io0 e2 nc nc io0 io0 e3 nc nc io0 io0 e4 io0 io0 io0 io0 e5 gnd gnd gnd gnd e6 io7 io7 io7 io7 e7 io7 io7 io7 io7 e8 io7 io7 io7 io7 e9 v ccio7 v ccio7 v ccio7 v ccio7 e10 v cc v cc v cc v cc e11 io/v ref7 io/v ref7 io/v ref7 io/v ref7 e12 nc io/v ref6 io/v ref6 io/v ref6 e13 v ccpll v ccpll v ccpll v ccpll e14 v ccio6 v ccio6 v ccio6 v ccio6 e15 nc io6 io6 [19] io6 e16 nc io6 io6 io6 e17 nc io6 io6 io6 e18 gnd gnd gnd gnd e19 tdo tdo tdo tdo e20 nc nc io5 io5 e21 nc nc io5 io5 e22 nc nc io5 io5 f1 nc nc io0 io0 f2 nc io0 io0 io0 f3 io0 io0 io0 io0 f4 io0 io0 io0 io0 f5 io0 io0 io0 io0 f6 gnd gnd gnd gnd table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 69 of 86 f7 io7 io7 io7 io7 f8 io7 io7 io7 io7 f9 v ccio7 v ccio7 v ccio7 v ccio7 f10 v ccio7 v ccio7 v ccio7 v ccio7 f11 [19] io7 io7 io7 io7 f12 [19] io6 io6 io6 io6 f13 v ccio6 v ccio6 v ccio6 v ccio6 f14 v ccio6 v ccio6 v ccio6 v ccio6 f15 io6 io6 io6 io6 f16 nc io6 io6 io6 f17 gnd gnd gnd gnd f18 tdi tdi tdi tdi f19 io5 io5 io5 io5 f20 io5 io5 io5 io5 f21 nc io5 io5 io5 f22 nc nc io5 io5 g1 nc nc io0 io0 g2 io0 io0 io0 io0 g3 nc io0 io0 io0 g4 io0 io0 io0 io0 g5 io0 io0 io0 io0 g6 io0 io0 io0 io0 g7 gnd gnd gnd gnd g8 io7 io7 io7 io7 g9 nc io/v ref7 io/v ref7 io/v ref7 g10 io7 io7 io7 io7 g11 [19] io7 io7 io7 io7 g12 [19] io6 io6 io6 io6 g13 io6 io6 io6 [20] io6 g14 io/v ref6 io/v ref6 io/v ref6 io/v ref6 g15 io6 io6 io6 io6 g16 gnd gnd gnd gnd g17 tclk tclk tclk tclk g18 io5 io5 io5 io5 g19 io5 io5 io5 io5 g20 io5 io5 io5 io5 g21 io5 io5 io5 io5 g22 nc nc io5 io5 h1 nc nc io0 io0 h2 io0 io0 io0 io0 h3 io0 io0 io0 io0 h4 io0 io0 io0 io0 h5 nc io0 io0 io0 h6 nc io0 io0 io0 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 70 of 86 h7 nc io0 io0 io0 h8 io7 io7 io7 io7 h9 io7 io7 io7 io7 h10 io7 io7 io7 io7 h11 [19] io7 io7 io7 io7 h12 [19] io6 io6 io6 io6 h13 io6 io6 io6 io6 h14 io6 io6 io6 io6 h15 tms tms tms tms h16 io5 io5 io5 io5 h17 io5 io5 io5 io5 h18 io5 io5 io5 io5 h19 io5 io5 io5 io5 h20 io5 io5 io5 io5 h21 io5 io5 io5 io5 h22 nc nc io5 io5 j1 nc nc io/v ref0 io/v ref0 j2 nc nc vccio0 vccio0 j3 nc io/v ref0 io/v ref0 io/v ref0 j4 nc io0 io0 io0 j5 nc v cc v cc v cc j6 v ccio0 v ccio0 v ccio0 v ccio0 j7 io/v ref0 io/v ref0 io/v ref0 io/v ref0 j8 nc io0 io0 io0 j9 io7 io7 io7 io7 j10 gctl3 gctl3 gctl3 gctl3 j11 gclk3 gclk3 gclk3 gclk3 j12 gctl2 gctl2 gctl2 gctl2 j13 gclk2 gclk2 gclk2 gclk2 j14 io5 io5 io5 io5 j15 io5 io5 io5 io5 j16 io/v ref5 io/v ref5 io/v ref5 io/v ref5 j17 v ccio5 v ccio5 v ccio5 v ccio5 j18 v ccjtag v ccjtag v ccjtag v ccjtag j19 nc io5 io5 io5 j20 nc io/v ref5 io/v ref5 io/v ref5 j21 nc nc v ccio5 v ccio5 j22 nc nc io/v ref5 io/v ref5 k1 nc nc io0 io0 k2 io0 io0 io0 io0 k3 nc io0 io0 io0 k4 io0 io0 io0 io0 k5 v cc v cc v cc v cc k6 v ccio0 v ccio0 v ccio0 v ccio0 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 71 of 86 k7 io/v ref0 io/v ref0 io/v ref0 io/v ref0 k8 nc io0 io0 io0 k9 gctl0 gctl0 gctl0 gctl0 k10 gnd gnd gnd gnd k11 gnd gnd gnd gnd k12 gnd gnd gnd gnd k13 gnd gnd gnd gnd k14 gctl1 gctl1 gctl1 gctl1 k15 nc io5 io5 io5 k16 io/v ref5 io/v ref5 io/v ref5 io/v ref5 k17 v ccio5 v ccio5 v ccio5 v ccio5 k18 nc v cc v cc v cc k19 nc io5 io5 io5 k20 nc io5 io5 io5 k21 nc io5 io5 io5 k22 nc nc io5 io5 l1 gnd gnd gnd gnd l2 io0 io0 io0 io0 l3 io0 io0 io0 io0 l4 [19] io0 io0 io0 io0 l5 [19] io0 io0 io0 io0 l6 [19] io0 io0 io0 io0 l7 io/v ref0 io/v ref0 io/v ref0 io/v ref0 l8 nc io0 io0 io0 l9 gclk0 gclk0 gclk0 gclk0 l10 gnd gnd gnd gnd l11 gnd gnd gnd gnd l12 gnd gnd gnd gnd l13 gnd gnd gnd gnd l14 gclk1 gclk1 gclk1 gclk1 l15 nc io5 io5 io5 l16 io/v ref5 io/v ref5 io/v ref5 io/v ref5 l17 [19] io5 io5 io5 io5 l18 [19] io5 io5 io5 io5 l19 [19] io5 io5 io5 io5 l20 io5 io5 io5 io5 l21 nc io5 io5 io5 l22 gnd gnd gnd gnd m1 gnd gnd gnd gnd m2 nc io1 io1 io1 m3 io1 io1 io1 io1 m4 io1 io1 io1 io1 m5 nc io1 io1 io1 m6 [19] io1 io1 io1 io1 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 72 of 86 m7 [19] io1 io1 io1 io1 m8 [19] io1 io1 io1 io1 m9 io1 io1 io1 io1 m10 gnd gnd gnd gnd m11 gnd gnd gnd gnd m12 gnd gnd gnd gnd m13 gnd gnd gnd gnd m14 io4 io4 io4 io4 m15 [19] io4 io4 io4 io4 m16 [19] io4 io4 io4 io4 m17 [19] io4 io4 io4 io4 m18 nc io5 io5 io5 m19 nc io5 io5 io5 m20 io4 io4 io4 io4 m21 io4 io4 io4 io4 m22 gnd gnd gnd gnd n1 nc nc io1 io1 n2 nc io1 io1 io1 n3 nc io1 io1 io1 n4 nc io1 io1 io1 n5 v ccprg v ccprg v ccprg v ccprg n6 v ccio1 v ccio1 v ccio1 v ccio1 n7 io/v ref1 io/v ref1 io/v ref1 io/v ref1 n8 nc io1 io1 io1 n9 nc io1 io1 io1 n10 gnd gnd gnd gnd n11 gnd gnd gnd gnd n12 gnd gnd gnd gnd n13 gnd gnd gnd gnd n14 nc io4 io4 io4 n15 io4 io4 io4 io4 n16 io/v ref4 io/v ref4 io/v ref4 io/v ref4 n17 v ccio4 v ccio4 v ccio4 v ccio4 n18 v ccprg v ccprg v ccprg v ccprg n19 nc io4 io4 io4 n20 nc io4 io4 io4 n21 nc io4 io4 io4 n22 nc nc io4 io4 p1 nc nc io/v ref1 io/v ref1 p2 nc nc v ccio1 v ccio1 p3 io/v ref1 io/v ref1 io/v ref1 io/v ref1 p4 nc io1 io1 io1 p5 v cc v cc v cc v cc p6 v ccio1 v ccio1 v ccio1 v ccio1 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 73 of 86 p7 nc io/v ref1 io/v ref1 io/v ref1 p8 v cccnfg v cccnfg v cccnfg v cccnfg p9 config_done config_done config_done config_done p10 io2 io2 io2 io2 p11 [19] io2 io2 io2 io2 p12 [19] io3 io3 io3 io3 p13 io3 io3 io3 io3 p14 io3 io3 io3 io3 p15 nc io4 io4 io4 p16 io/v ref4 io/v ref4 io/v ref4 io/v ref4 p17 v ccio4 v ccio4 v ccio4 v ccio4 p18 v cc v cc v cc v cc p19 nc io4 io4 io4 p20 nc io/v ref4 io/v ref4 io/v ref4 p21 nc nc v ccio4 v ccio4 p22 nc nc io/v ref4 io/v ref4 r1 nc nc io1 io1 r2 nc io1 io1 io1 r3 io1 io1 io1 io1 r4 io1 io1 io1 io1 r5 io1 io1 io1 io1 r6 io1 io1 io1 io1 r7 data data data data r8 reconfig reconfig reconfig reconfig r9 io2 io2 io2 io2 r10 io2 io2 io2 io2 r11 [19] io2 io2 io2 io2 r12 [19] io3 io3 io3 io3 r13 io3 io3 io3 io3 r14 io3 io3 io3 io3 r15 nc io3 io3 io3 r16 nc io4 io4 io4 r17 nc io4 io4 io4 r18 nc io4 io4 io4 r19 io4 io4 io4 io4 r20 io4 io4 io4 io4 r21 io4 io4 io4 io4 r22 nc nc io4 io4 t1 nc nc io1 io1 t2 io1 io1 io1 io1 t3 io1 io1 io1 io1 t4 io/v ref1 io/v ref1 io/v ref1 io/v ref1 t5 io1 io1 io1 io1 t6 io1 io1 io1 io1 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 74 of 86 t7 gnd gnd gnd gnd t8 msel msel msel msel t9 io/v ref2 io/v ref2 io/v ref2 io/v ref2 t10 io/v ref2 io/v ref2 io/v ref2 io/v ref2 t11 [19] io2 io2 io2 io2 t12 [19] io3 io3 io3 io3 t13 io/v ref3 io/v ref3 io/v ref3 [20] io/v ref3 t14 io/v ref3 io/v ref3 io/v ref3 io/v ref3 t15 io3 io3 io3 io3 t16 gnd gnd gnd gnd t17 io4 io4 io4 io4 t18 io4 io4 io4 io4 t19 io/v ref4 io/v ref4 io/v ref4 io/v ref4 t20 io4 io4 io4 io4 t21 io4 io4 io4 io4 t22 nc nc io4 io4 u1 nc nc io1 io1 u2 io1 io1 io1 io1 u3 io1 io1 io1 io1 u4 io1 io1 io1 io1 u5 io1 io1 io1 io1 u6 gnd gnd gnd gnd u7 cce cce cce cce u8 io2 io2 io2 io2 u9 v ccio2 v ccio2 v ccio2 v ccio2 u10 v ccio2 v ccio2 v ccio2 v ccio2 u11 io2 io2 io2 io2 u12 io2 io2 io2 io2 u13 v ccio3 v ccio3 v ccio3 v ccio3 u14 v ccio3 v ccio3 v ccio3 v ccio3 u15 io3 io3 io3 [20] io3 u16 io3 io3 io3 io3 u17 gnd gnd gnd gnd u18 io4 io4 io4 io4 u19 io4 io4 io4 io4 u20 io4 io4 io4 io4 u21 io4 io4 io4 io4 u22 nc nc io4 io4 v1 nc nc io1 io1 v2 nc nc io1 io1 v3 nc nc io1 io1 v4 nc nc io1 io1 v5 gnd gnd gnd gnd v6 cclk cclk cclk cclk table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 75 of 86 v7 io2 io2 io2 io2 v8 nc io2 io2 io2 v9 v cccnfg v cccnfg v cccnfg v cccnfg v10 v ccio2 v ccio2 v ccio2 v ccio2 v11 io2 io2 io2 io2 v12 io2 io2 io2 io2 v13 nc v cc v cc v cc v14 v ccio3 v ccio3 v ccio3 v ccio3 v15 io3 io3 io3 io3 v16 io3 io3 io3 io3 v17 io3 io3 io3 io3 v18 gnd gnd gnd gnd v19 nc nc io4 io4 v20 nc nc io4 io4 v21 nc nc io4 io4 v22 nc nc io4 io4 w1 nc nc io/v ref1 io/v ref1 w2 v ccio1 v ccio1 v ccio1 v ccio1 w3 nc nc io1 io1 w4 gnd gnd gnd gnd w5 reset reset reset reset w6 io2 io2 io2 io2 w7 nc io2 io2 io2 w8 io2 io2 io2 io2 w9 nc io/v ref2 io/v ref2 io/v ref2 w10 nc io/v ref2 io/v ref2 io/v ref2 w11 io2 io2 io2 io2 w12 io2 io2 io2 io2 w13 nc io/v ref3 io/v ref3 io/v ref3 w14 nc io/v ref3 io/v ref3 io/v ref3 w15 io3 io3 io3 io3 w16 io3 io3 io3 io3 w17 io3 io3 io3 io3 w18 nc io3 io3 io3 w19 gnd gnd gnd gnd w20 nc nc io4 io4 w21 v ccio4 v ccio4 v ccio4 v ccio4 w22 nc nc io/v ref4 io/v ref4 y1 nc nc io2 io2 y2 nc nc io2 io2 y3 nc nc io2 io2 y4 io2 io2 io2 io2 y5 io2 io2 io2 io2 y6 io2 io2 io2 io2 table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 76 of 86 y7 io2 io2 io2 io2 y8 nc io2 io2 io2 y9 nc io2 io2 io2 y10 io/v ref2 io/v ref2 io/v ref2 io/v ref2 y11 io2 io2 io2 io2 y12 io3 io3 io3 io3 y13 io/v ref3 io/v ref3 io/v ref3 io/v ref3 y14 io3 io3 io3 io3 y15 io3 io3 io3 io3 y16 io3 io3 io3 io3 y17 io3 io3 io3 io3 y18 nc io3 io3 io3 y19 nc io3 io3 io3 y20 nc nc nc io3 y21 nc nc nc io3 y22 nc nc nc io3 aa1 gnd gnd gnd gnd aa2 gnd gnd gnd gnd aa3 nc nc io2 io2 aa4 v ccio2 v ccio2 v ccio2 v ccio2 aa5 io/v ref2 io/v ref2 io/v ref2 io/v ref2 aa6 io2 io2 io2 io2 aa7 nc io2 io2 io2 aa8 io2 io2 io2 io2 aa9 nc nc v ccio2 v ccio2 aa10 nc io2 io2 io2 aa11 io2 io2 io2 io2 aa12 io3 io3 io3 io3 aa13 io3 io3 io3 io3 aa14 nc nc v ccio3 v ccio3 aa15 io3 io3 io3 io3 aa16 nc io3 io3 [20] io3 aa17 nc io3 io3 [20] io3 aa18 io/v ref3 io/v ref3 io/v ref3 io/v ref3 aa19 v ccio3 v ccio3 v ccio3 v ccio3 aa20 nc nc nc io3 aa21 gnd gnd gnd gnd aa22 gnd gnd gnd gnd ab1 gnd gnd gnd gnd ab2 gnd gnd gnd gnd ab3 nc nc io/v ref2 io/v ref2 ab4 nc nc io/v ref2 io/v ref2 note: 20. these i/os have a slightly higher t pd (propagation delay) than the rest of the pins. the use of these pins on the same packages of different densities or the pins in the same relative position in smaller or larger fbgas for signals with critical timing should be avoided. when first im plementing a design in these packages, the timing-driven routing of warp 6.2 and later versions will ensure these pins are avoided when routing critical signal. table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 77 of 86 ab5 io2 io2 io2 io2 ab6 io2 io2 io2 io2 ab7 io2 io2 io2 io2 ab8 nc io2 io2 io2 ab9 nc io2 io2 io2 ab10 nc io2 io2 io2 ab11 gnd gnd gnd gnd ab12 gnd gnd gnd gnd ab13 io3 io3 io3 io3 ab14 io3 io3 io3 io3 ab15 io3 io3 io3 io3 ab16 nc io3 io3 io3 ab17 io3 io3 io3 io3 ab18 nc io3 io3 io3 ab19 nc nc nc io/v ref3 ab20 nc nc nc io3 ab21 gnd gnd gnd gnd ab22 gnd gnd gnd gnd table 14. 484 fbga pin table (continued) pin cy39050 cy39100 cy39165 cy39200 table 15. 676 fbga pin table pin cy39100 cy39165 cy39200 a1 gnd gnd gnd a2 nc nc nc a3 nc io7 io7 a4 nc io7 io7 a5 nc io7 io7 a6 nc v ccio7 v ccio7 a7 nc io7 io7 a8 nc io7 io7 a9 nc io7 io7 a10 nc nc nc a11 nc v ccio7 v ccio7 a12 nc nc nc a13 gnd gnd gnd a14 gnd gnd gnd a15 nc nc nc a16 nc v ccio6 v ccio6 a17 nc nc nc a18 nc nc io6 a19 nc nc io6 a20 nc nc io6 a21 nc v ccio6 v ccio6 a22 nc nc io6 a23 nc nc io6 a24 nc nc io6 a25 nc nc nc a26 gnd gnd gnd b1 nc nc nc b2 gnd gnd gnd b3 nc io7 io7 b4 nc io7 io7 b5 nc io7 io7 b6 nc nc nc b7 nc io7 io7 b8 nc io7 io7 b9 nc io7 io7 b10 nc io7 io7 b11 nc io7 io7 b12 nc io7 io7 b13 gnd gnd gnd b14 gnd gnd gnd b15 nc nc io6 b16 nc nc io6 b17 nc nc io6 b18 nc nc io6 b19 nc nc io6 b20 nc nc io6 b21 nc nc io/v ref6 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 78 of 86 b22 nc nc io6 b23 nc nc io6 b24 nc nc nc b25 gnd gnd gnd b26 nc nc nc c1 nc nc nc c2 nc nc nc c3 gnd gnd gnd c4 gnd gnd gnd c5 nc io/v ref7 io/v ref7 c6 nc io/v ref7 io/v ref7 c7 io7 io7 io7 c8 io7 io7 io7 c9 io7 io7 io7 c10 io7 io7 io7 c11 io7 io7 io7 c12 io7 io7 io7 c13 gnd gnd gnd c14 gnd gnd gnd c15 io6 io6 io6 c16 io6 io6 io6 c17 io6 io6 [20] io6 c18 io6 io6 [20] io6 c19 io6 io6 io6 c20 io6 io6 io6 c21 nc nc io/v ref6 c22 nc nc io6 c23 gnd gnd gnd c24 gnd gnd gnd c25 nc nc nc c26 nc nc nc d1 nc nc nc d2 nc nc nc d3 gnd gnd gnd d4 gnd gnd gnd d5 nc io7 io7 d6 v ccio7 v ccio7 v ccio7 d7 io7 io7 io7 d8 io7 io7 io7 d9 io7 io7 io7 d10 io/v ref7 io/v ref7 io/v ref7 d11 nc v ccio7 v ccio7 d12 io7 io7 io7 d13 io7 io7 io7 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 d14 io6 io6 io6 d15 io6 io6 io6 d16 nc v ccio6 v ccio6 d17 io/v ref6 io/v ref6 io/v ref6 d18 io6 io6 [20] io6 d19 io6 io6 io6 d20 io6 io6 io6 d21 v ccio6 v ccio6 v ccio6 d22 nc nc io6 d23 gnd gnd gnd d24 gnd gnd gnd d25 nc nc nc d26 nc nc nc e1 nc nc nc e2 nc nc nc e3 nc io7 io7 e4 nc io7 io7 e5 nc io7 io7 e6 io7 io7 io7 e7 io7 io7 io7 e8 io7 io7 io7 e9 io7 io7 io7 e10 io7 io7 io7 e11 io7 io7 io7 e12 io/v ref7 io/v ref7 io/v ref7 e13 io7 io7 io7 e14 io6 io6 io6 e15 io/v ref6 io/v ref6 io/v ref6 e16 io6 io6 io6 e17 io6 io6 [20] io6 e18 io6 io6 [20] io6 e19 io6 io6 io6 e20 io6 io6 io6 e21 io6 io6 io6 e22 nc nc io6 e23 nc nc io6 e24 nc nc io6 e25 nc nc nc e26 nc nc nc f1 nc nc nc f2 nc nc nc f3 nc io/v ref0 io/v ref0 f4 v ccio0 v ccio0 v ccio0 f5 nc io0 io0 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 79 of 86 f6 gnd gnd gnd f7 io7 io7 io7 f8 io7 io7 io7 f9 io7 io7 io7 f10 io7 io7 io7 f11 io/v ref7 io/v ref7 io/v ref7 f12 io/v ref7 io/v ref7 io/v ref7 f13 io6/lock io6/lock io6/lock f14 io6 io6 io6 f15 io/v ref6 io/v ref6 io/v ref6 f16 io/v ref6 io/v ref6 io/v ref6 f17 io6 io6 io6 f18 io6 io6 io6 f19 io6 io6 io6 f20 io6 io6 io6 f21 gnd gnd gnd f22 nc io5 io5 f23 v ccio5 v ccio5 v ccio5 f24 nc io/v ref5 io/v ref5 f25 nc nc nc f26 nc nc nc g1 nc nc nc g2 nc nc nc g3 nc io0 io0 g4 nc io0 io0 g5 nc io0 io0 g6 io0 io0 io0 g7 gnd gnd gnd g8 io7 io7 io7 g9 io7 io7 io7 g10 io7 io7 io7 g11 v ccio7 v ccio7 v ccio7 g12 v cc v cc v cc g13 io/v ref7 io/v ref7 io/v ref7 g14 io/v ref6 io/v ref6 io/v ref6 g15 v ccpll v ccpll v ccpll g16 v ccio6 v ccio6 v ccio6 g17 io6 io6 [20] io6 g18 io6 io6 io6 g19 io6 io6 io6 g20 gnd gnd gnd g21 tdo tdo tdo g22 nc io5 io5 g23 nc io5 io5 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 g24 nc io5 io5 g25 nc nc nc g26 nc nc nc h1 nc nc nc h2 nc nc nc h3 nc io0 io0 h4 io0 io0 io0 h5 io0 io0 io0 h6 io0 io0 io0 h7 io0 io0 io0 h8 gnd gnd gnd h9 io7 io7 io7 h10 io7 io7 io7 h11 v ccio7 v ccio7 v ccio7 h12 v ccio7 v ccio7 v ccio7 h13 [19] io7 io7 io7 h14 [19] io6 io6 io6 h15 v ccio6 v ccio6 v ccio6 h16 v ccio6 v ccio6 v ccio6 h17 io6 io6 io6 h18 io6 io6 [20] io6 h19 gnd gnd gnd h20 tdi tdi tdi h21 io5 io5 io5 h22 io5 io5 io5 h23 io5 io5 io5 h24 nc io5 io5 h25 nc nc nc h26 nc nc nc j1 nc nc nc j2 nc nc nc j3 nc io0 io0 j4 io0 io0 io0 j5 io0 io0 io0 j6 io0 io0 io0 j7 io0 io0 io0 j8 io0 io0 io0 j9 gnd gnd gnd j10 io7 io7 io7 j11 io/v ref7 io/v ref7 io/v ref7 j12 io7 io7 io7 j13 [19] io7 io7 io7 j14 [19] io6 io6 io6 j15 io6 io6 io6 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 80 of 86 j16 io/v ref6 io/v ref6 io/v ref6 j17 io6 io6 io6 j18 gnd gnd gnd j19 tclk tclk tclk j20 io5 io5 io5 j21 io5 io5 io5 j22 io5 io5 io5 j23 io5 io5 io5 j24 nc io5 io5 j25 nc nc nc j26 nc nc nc k1 nc nc nc k2 nc nc nc k3 nc io0 io0 k4 io0 io0 io0 k5 io0 io0 io0 k6 io0 io0 io0 k7 io0 io0 io0 k8 io0 io0 io0 k9 io0 io0 io0 k10 io7 io7 io7 k11 io7 io7 io7 k12 io7 io7 io7 k13 [19] io7 io7 io7 k14 [19] io6 io6 io6 k15 io6 io6 io6 k16 io6 io6 [20] io6 k17 tms tms tms k18 io5 io5 io5 k19 io5 io5 io5 k20 io5 io5 io5 k21 io5 io5 io5 k22 io5 io5 io5 k23 io5 io5 io5 k24 nc io5 io5 k25 nc nc nc k26 nc nc nc l1 nc nc nc l2 nc nc nc l3 nc io/v ref0 io/v ref0 l4 nc v ccio0 v ccio0 l5 io/v ref0 io/v ref0 io/v ref0 l6 io0 io0 io0 l7 v cc v cc v cc table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 l8 v ccio0 v ccio0 v ccio0 l9 io/v ref0 io/v ref0 io/v ref0 l10 io0 io0 io0 l11 io7 io7 io7 l12 gctl3 gctl3 gctl3 l13 gclk3 gclk3 gclk3 l14 gctl2 gctl2 gctl2 l15 gclk2 gclk2 gclk2 l16 io5 io5 io5 l17 io5 io5 io5 l18 io/v ref5 io/v ref5 io/v ref5 l19 v ccio5 v ccio5 v ccio5 l20 v ccjtag v ccjtag v ccjtag l21 io5 io5 io5 l22 io/v ref5 io/v ref5 io/v ref5 l23 nc v ccio5 v ccio5 l24 nc io/v ref5 io/v ref5 l25 nc nc nc l26 nc nc nc m1 nc nc nc m2 nc nc nc m3 nc io0 io0 m4 io0 io0 io0 m5 io0 io0 io0 m6 io0 io0 io0 m7 v cc v cc v cc m8 v ccio0 v ccio0 v ccio0 m9 io/v ref0 io/v ref0 io/v ref0 m10 io0 io0 io0 m11 gctl0 gctl0 gctl0 m12 gnd gnd gnd m13 gnd gnd gnd m14 gnd gnd gnd m15 gnd gnd gnd m16 gctl1 gctl1 gctl1 m17 io5 io5 io5 m18 io/v ref5 io/v ref5 io/v ref5 m19 v ccio5 v ccio5 v ccio5 m20 v cc v cc v cc m21 io5 io5 io5 m22 io5 io5 io5 m23 io5 io5 io5 m24 nc io5 io5 m25 nc nc nc table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 81 of 86 m26 nc nc nc n1 gnd gnd gnd n2 gnd gnd gnd n3 gnd gnd gnd n4 io0 io0 io0 n5 io0 io0 io0 n6 [19] io0 io0 io0 n7 [19] io0 io0 io0 n8 [19] io0 io0 io0 n9 io/v ref0 io/v ref0 io/v ref0 n10 io0 io0 io0 n11 gclk0 gclk0 gclk0 n12 gnd gnd gnd n13 gnd gnd gnd n14 gnd gnd gnd n15 gnd gnd gnd n16 gclk1 gclk1 gclk1 n17 io5 io5 io5 n18 io/v ref5 io/v ref5 io/v ref5 n19 [19] io5 io5 io5 n20 [19] io5 io5 io5 n21 [19] io5 io5 io5 n22 io5 io5 io5 n23 io5 io5 io5 n24 gnd gnd gnd n25 gnd gnd gnd n26 gnd gnd gnd p1 gnd gnd gnd p2 gnd gnd gnd p3 gnd gnd gnd p4 io1 io1 io1 p5 io1 io1 io1 p6 io1 io1 io1 p7 io1 io1 io1 p8 [19] io1 io1 io1 p9 [19] io1 io1 io1 p10 [19] io1 io1 io1 p11 io1 io1 io1 p12 gnd gnd gnd p13 gnd gnd gnd p14 gnd gnd gnd p15 gnd gnd gnd p16 io4 io4 io4 p17 [19] io4 io4 io4 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 p18 [19] io4 io4 io4 p19 [19] io4 io4 io4 p20 io5 io5 io5 p21 io5 io5 io5 p22 io4 io4 io4 p23 io4 io4 io4 p24 gnd gnd gnd p25 gnd gnd gnd p26 gnd gnd gnd r1 nc nc nc r2 nc nc nc r3 nc io1 io1 r4 io1 io1 io1 r5 io1 io1 io1 r6 io1 io1 io1 r7 v ccprg v ccprg v ccprg r8 v ccio1 v ccio1 v ccio1 r9 io/v ref1 io/v ref1 io/v ref1 r10 io1 io1 io1 r11 io1 io1 io1 r12 gnd gnd gnd r13 gnd gnd gnd r14 gnd gnd gnd r15 gnd gnd gnd r16 io4 io4 io4 r17 io4 io4 io4 r18 io/v ref4 io/v ref4 io/v ref4 r19 v ccio4 v ccio4 v ccio4 r20 v ccprg v ccprg v ccprg r21 io4 io4 io4 r22 io4 io4 io4 r23 io4 io4 io4 r24 nc io4 io4 r25 nc nc nc r26 nc nc nc t1 nc nc nc t2 nc nc nc t3 nc io/v ref1 io/v ref1 t4 nc v ccio1 v ccio1 t5 io/v ref1 io/v ref1 io/v ref1 t6 io1 io1 io1 t7 v cc v cc v cc t8 v ccio1 v ccio1 v ccio1 t9 io/v ref1 io/v ref1 io/v ref1 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 82 of 86 t10 v cccnfg v cccnfg v cccnfg t11 config_done config_done config_done t12 io2 io2 io2 t13 [19] io2 io2 io2 t14 [19] io3 io3 io3 t15 io3 io3 io3 t16 io3 io3 io3 t17 io4 io4 io4 t18 io/v ref4 io/v ref4 io/v ref4 t19 v ccio4 v ccio4 v ccio4 t20 v cc v cc v cc t21 io4 io4 io4 t22 io/v ref4 io/v ref4 io/v ref4 t23 nc v ccio4 v ccio4 t24 nc io/v ref4 io/v ref4 t25 nc nc nc t26 nc nc nc u1 nc nc nc u2 nc nc nc u3 nc io1 io1 u4 nc io1 io1 u5 io1 io1 io1 u6 io1 io1 io1 u7 io1 io1 io1 u8 io1 io1 io1 u9 data data data u10 reconfig reconfig reconfig u11 io2 io2 io2 u12 io2 io2 io2 u13 [19] io2 io2 io2 u14 [19] io3 io3 io3 u15 io3 io3 io3 u16 io3 io3 io3 u17 io3 io3 io3 u18 io4 io4 io4 u19 io4 io4 io4 u20 io4 io4 io4 u21 io4 io4 io4 u22 io4 io4 io4 u23 nc io4 io4 u24 nc io4 io4 u25 nc nc nc u26 nc nc nc v1 nc nc nc table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 v2 nc nc nc v3 nc io1 io1 v4 io1 io1 io1 v5 io1 io1 io1 v6 io/v ref1 io/v ref1 io/v ref1 v7 io1 io1 io1 v8 io1 io1 io1 v9 gnd gnd gnd v10 msel msel msel v11 io/v ref2 io/v ref2 io/v ref2 v12 io/v ref2 io/v ref2 io/v ref2 v13 [19] io2 io2 io2 v14 [19] io3 io3 io3 v15 io/v ref3 io/v ref3 [20] io/v ref3 v16 io/v ref3 io/v ref3 io/v ref3 v17 io3 io3 io3 v18 gnd gnd gnd v19 io4 io4 io4 v20 io4 io4 io4 v21 io/v ref4 io/v ref4 io/v ref4 v22 io4 io4 io4 v23 io4 io4 io4 v24 nc io4 io4 v25 nc nc nc v26 nc nc nc w1 nc nc nc w2 nc nc nc w3 nc io1 io1 w4 io1 io1 io1 w5 io1 io1 io1 w6 io1 io1 io1 w7 io1 io1 io1 w8 gnd gnd gnd w9 cce cce cce w10 io2 io2 io2 w11 v ccio2 v ccio2 v ccio2 w12 v ccio2 v ccio2 v ccio2 w13 io2 io2 io2 w14 io2 io2 io2 w15 v ccio3 v ccio3 v ccio3 w16 v ccio3 v ccio3 v ccio3 w17 io3 io3 io3 w18 io3 io3 io3 w19 gnd gnd gnd table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 83 of 86 w20 io4 io4 io4 w21 io4 io4 io4 w22 io4 io4 io4 w23 io4 io4 io4 w24 nc io4 io4 w25 nc nc nc w26 nc nc nc y1 nc nc nc y2 nc nc nc y3 nc io1 io1 y4 nc io1 io1 y5 nc io1 io1 y6 io1 io1 io1 y7 gnd gnd gnd y8 cclk cclk cclk y9 io2 io2 io2 y10 io2 io2 io2 y11 v cccnfg v cccnfg v cccnfg y12 v ccio2 v ccio2 v ccio2 y13 io2 io2 io2 y14 io2 io2 io2 y15 v cc v cc v cc y16 v ccio3 v ccio3 v ccio3 y17 io3 io3 io3 y18 io3 io3 io3 y19 io3 io3 io3 y20 gnd gnd gnd y21 io4 io4 io4 y22 nc io4 io4 y23 nc io4 io4 y24 nc io4 io4 y25 nc nc nc y26 nc nc nc aa1 nc nc nc aa2 nc nc nc aa3 nc io/v ref1 io/v ref1 aa4 v ccio1 v ccio1 v ccio1 aa5 nc io1 io1 aa6 gnd gnd gnd aa7 reset reset reset aa8 io2 io2 io2 aa9 io2 io2 io2 aa10 io2 io2 io2 aa11 io/v ref2 io/v ref2 io/v ref2 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 aa12 io/v ref2 io/v ref2 io/v ref2 aa13 io2 io2 io2 aa14 io2 io2 io2 aa15 io/v ref3 io/v ref3 io/v ref3 aa16 io/v ref3 io/v ref3 io/v ref3 aa17 io3 io3 io3 aa18 io3 io3 io3 aa19 io3 io3 io3 aa20 io3 io3 io3 aa21 gnd gnd gnd aa22 nc io4 io4 aa23 v ccio4 v ccio4 v ccio4 aa24 nc io/v ref4 io/v ref4 aa25 nc nc nc aa26 nc nc nc ab1 nc nc nc ab2 nc nc nc ab3 nc io2 io2 ab4 nc io2 io2 ab5 nc io2 io2 ab6 io2 io2 io2 ab7 io2 io2 io2 ab8 io2 io2 io2 ab9 io2 io2 io2 ab10 io2 io2 io2 ab11 io2 io2 io2 ab12 io/v ref2 io/v ref2 io/v ref2 ab13 io2 io2 io2 ab14 io3 io3 io3 ab15 io/v ref3 io/v ref3 io/v ref3 ab16 io3 io3 io3 ab17 io3 io3 [20] io3 ab18 io3 io3 io3 ab19 io3 io3 io3 ab20 io3 io3 io3 ab21 io3 io3 io3 ab22 nc nc io3 ab23 nc nc io3 ab24 nc nc io3 ab25 nc nc nc ab26 nc nc nc ac1 nc nc nc ac2 nc nc nc ac3 gnd gnd gnd table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 84 of 86 ac4 gnd gnd gnd ac5 nc io2 io2 ac6 v ccio2 v ccio2 v ccio2 ac7 io/v ref2 io/v ref2 io/v ref2 ac8 io2 io2 io2 ac9 io2 io2 io2 ac10 io2 io2 io2 ac11 nc v ccio2 v ccio2 ac12 io2 io2 io2 ac13 io2 io2 io2 ac14 io3 io3 io3 ac15 io3 io3 io3 ac16 nc v ccio3 v ccio3 ac17 io3 io3 [20] io3 ac18 io3 io3 [20] io3 ac19 io3 io3 [20] io3 ac20 io/v ref3 io/v ref3 [20] io/v ref3 ac21 v ccio3 v ccio3 v ccio3 ac22 nc nc io3 ac23 gnd gnd gnd ac24 gnd gnd gnd ac25 nc nc nc ac26 nc nc nc ad1 nc nc nc ad2 nc nc nc ad3 gnd gnd gnd ad4 gnd gnd gnd ad5 nc io/v ref2 io/v ref2 ad6 nc io/v ref2 io/v ref2 ad7 io2 io2 io2 ad8 io2 io2 io2 ad9 io2 io2 io2 ad10 io2 io2 io2 ad11 io2 io2 io2 ad12 io2 io2 io2 ad13 gnd gnd gnd ad14 gnd gnd gnd ad15 io3 io3 io3 ad16 io3 io3 io3 ad17 io3 io3 [20] io3 ad18 io3 io3 [20] io3 ad19 io3 io3 io3 ad20 io3 io3 io3 ad21 nc nc io/v ref3 table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200 ad22 nc nc io3 ad23 gnd gnd gnd ad24 gnd gnd gnd ad25 nc nc nc ad26 nc nc nc ae1 nc nc nc ae2 gnd gnd gnd ae3 nc io2 io2 ae4 nc io2 io2 ae5 nc io2 io2 ae6 nc nc nc ae7 nc io2 io2 ae8 nc io2 io2 ae9 nc io2 io2 ae10 nc io2 io2 ae11 nc io2 io2 ae12 nc io2 io2 ae13 gnd gnd gnd ae14 gnd gnd gnd ae15 nc nc io3 ae16 nc nc io3 ae17 nc nc io3 ae18 nc nc io3 ae19 nc nc io3 ae20 nc nc io3 ae21 nc nc io/v ref3 ae22 nc nc io3 ae23 nc nc io3 ae24 nc nc nc ae25 gnd gnd gnd ae26 nc nc nc af1 gnd gnd gnd af2 nc nc nc af3 nc io2 io2 af4 nc io2 io2 af5 nc io2 io2 af6 nc v ccio2 v ccio2 af7 nc io2 io2 af8 nc io2 io2 af9 nc io2 io2 af10 nc nc nc af11 nc v ccio2 v ccio2 af12 nc nc nc table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr? cpld fami ly document #: 38-03039 rev. *h page 85 of 86 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. windows 95, windows 98, windows 2000, windows xp, and windows nt are trademarks of microsoft corporation. zbt is a trademark of idt. qdr is a trademark of micron, idt, and cypress semiconductor. warp is a registered trademark, and nobl, programmable interconnect matrix, pim, spread aware, anyvolt, self-boot, in-system reprogrammable, isr, ?cplds at fpga densities,? true vertical migration, and delta39k are tradem arks, of cypress semiconductor. all product and company names mentioned in this document are the trademarks of their respective holders. af13 gnd gnd gnd af14 gnd gnd gnd af15 nc nc nc af16 nc v ccio3 v ccio3 af17 nc nc nc af18 nc nc io3 af19 nc nc io3 af20 nc nc io3 af21 nc v ccio3 v ccio3 af22 nc nc io3 af23 nc nc io3 af24 nc nc io3 af25 nc nc nc af26 gnd gnd gnd table 15. 676 fbga pin table (continued) pin cy39100 cy39165 cy39200
delta39k? isr ? cpld fami ly document #: 38-03039 rev. *h page 86 of 86 document history page document title: delta39k? isr? cpld family cplds at fpga densities? document number: 38-03039 rev. ecn no. issue date orig. of change description of change ** 106503 05/30/01 szv change from spec #: 38-00830 to 38-03039 *a 107625 07/11/01 rn deleted 39k15 device and the associated -250-mhz bin specs deleted 144fbga package and associated part numbers changed esd spec from ?mil-std-883? to ?jedec eia/jesd22-a114-a? changed the prime bin for 39k50 and 39k30 from ?mhz? to ?233 mhz? changed the part ordering information accordingly updated the -233-mhz timing specs to match modified timing specs achieved by design (main affected params: t pd , t mcco , t ios , t scs , t scs2 , f max2 , t clmaa , t clmcyc2 , t chmcyc2 , t chmclk ) updated i/o standard timing delay specs and changed the default i/o standard from 3.3v pci to lvcmos added paragraph about delta39k being compactpci hot swap ready added x8 mode in the pll description added standby icc spec updated the recommended boot prom for 39k165/200 to be cy3lv002 instead of cy3lv020 *b 109681 11/16/01 rn updated delta39k family offering modified pll timing parameters t dwsa , t dwosa , t mccj , and t lock . added t induty parameter deleted exception to compactpci hot swap compliance regarding ?pci buffers....? added reference to app note ?hot socketing delta39k? revised compactpci hot swap specification r1.0 to be r2.0 *c 112376 12/21/01 rn combined with spec# 38-03040 *d 112946 04/04/02 rn updated pin tables for 39k30 (208pqfp, 256fbga) updated pin tables for 39k50 (208pqfp, 256/484fbga, 388bga) added x3, x5, x6, x16 multiplication modes to spread aware pll added pll parameters (f pllvco , p saplli , f mppli ) added and updated storage temperature for 39k200-208eqfp changed the i cc0 spec for 39k165 and 39k200 updated tclz, tchmcyc2 parameter values for -233 mhz bin updated input and output standard timing delay adjustment table removed self boot industrial parts from the offering removed delta39k165z (1.8v) from the offering removed 144-fbga package offering added self-boot flash memory endurance and data retention data added family, package, and density migration section added note 20 to 484/676 fbga pin table to identify slow 39k165 ios *e 117518 10/04/02 oor changed data sheet status from preliminary to final added note 7 to dc characteristics *f 121063 11/06/02 dsg updated spec 51-85103 (mg388 package drawing) to rev. *c *g 122543 12/10/02 rn changed the definition of following pins on cy39030 -256fbga package: pin a10: from io/vref7 to io/vref6 pin b7: from io/vref6 to v cc added table to identify bank location of global clock and global control pins *h 128684 08/04/03 oor removed all ?z? parts (1.8v) referenced eeprom to atmel part number

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